From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-eopbgr70074.outbound.protection.outlook.com [40.107.7.74]) by dpdk.org (Postfix) with ESMTP id 1A27D1B94E for ; Thu, 18 Apr 2019 13:32:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0IWvHhWc2Vj+qm0b21Q7YX92srqQbrbcUCw4UsbXJkI=; b=OjqvGliL9IKAtazafJUVlesOqoHGTkUX/Q+12i/ydve3moidKHYv3F8Mb2dJXbWQURdReV62J/VprtePB371ZSRpF6RePBzFxgz6hKOltCdzAkOL5KKc6qD2EKc0ysKrq9DA/1FaxqFWE+n37OcKNBlloGg5jUvkidPg+0/0cao= Received: from AM0PR0502MB3971.eurprd05.prod.outlook.com (52.133.40.151) by AM0PR0502MB3810.eurprd05.prod.outlook.com (52.133.47.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1813.12; Thu, 18 Apr 2019 11:32:32 +0000 Received: from AM0PR0502MB3971.eurprd05.prod.outlook.com ([fe80::7da6:9e13:922a:9d88]) by AM0PR0502MB3971.eurprd05.prod.outlook.com ([fe80::7da6:9e13:922a:9d88%5]) with mapi id 15.20.1813.013; Thu, 18 Apr 2019 11:32:32 +0000 From: Yongseok Koh To: Hemant Agrawal , Honnappa Nagarahalli CC: "bruce.richardson@intel.com" , "jerinj@marvell.com" , "pbhagavatula@marvell.com" , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "Gavin Hu (Arm Technology China)" , nd Thread-Topic: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache line size for armv8 Thread-Index: AQHU9cATrNlj8cLQjUildp2P3jR4HKZByVGA Date: Thu, 18 Apr 2019 11:32:32 +0000 Message-ID: <62E7B12F-C840-454E-B7E7-9DA9734384C0@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190418014726.20600-1-yskoh@mellanox.com> <20190418014726.20600-2-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f4f57ba3-5468-41c4-ed60-08d6c3f18c59 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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bruce.richardson@intel.com; jerinj@marvell.com; >> pbhagavatula@marvell.com; shahafs@mellanox.com >> Cc: dev@dpdk.org; thomas@monjalon.net; Gavin Hu (Arm Technology >> China) ; Honnappa Nagarahalli >> ; nd ; nd >> Subject: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache >> line size for armv8 >>=20 >=20 >>>=20 >>> Currently, the cache line size of armv8 CPUs having Implementor ID of >>> 0x41 is >>> 64 bytes. >> I guess you meant to say 128 bytes >=20 >=20 > "the current default is 128, changing it to 64." Yep, the message was wrong. Will fix it. >>> Signed-off-by: Yongseok Koh >>> --- >>>=20 >>> v2: >>> * introduce flags_arm replacing flags_generic instead of using the >>> extra flags >>>=20 >>> config/arm/meson.build | 7 ++++++- >>> 1 file changed, 6 insertions(+), 1 deletion(-) >>>=20 >>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>> 22a062bad9..1db4ad2ee7 100644 >>> --- a/config/arm/meson.build >>> +++ b/config/arm/meson.build >>> @@ -32,6 +32,11 @@ flags_generic =3D [ >>> ['RTE_MAX_LCORE', 256], >>> ['RTE_USE_C11_MEM_MODEL', true], >>> ['RTE_CACHE_LINE_SIZE', 128]] >>> +flags_arm =3D [ >>> + ['RTE_MACHINE', '"armv8a"'], >>> + ['RTE_MAX_LCORE', 256], >> I am not aware of any implementations with implementor ID 0x41. Bluefiel= d >> is the first one I am aware of. May be we can keep this smaller, 16? >=20 > NXP also support implementer as 0x41, 16 will be good.=20 BlueField has 16 cores so yes, it is good. Thanks, Yongseok >=20 >>=20 >>> + ['RTE_USE_C11_MEM_MODEL', true], >>> + ['RTE_CACHE_LINE_SIZE', 64]] >>> flags_cavium =3D [ >>> ['RTE_CACHE_LINE_SIZE', 128], >>> ['RTE_MAX_NUMA_NODES', 2], >>> @@ -88,7 +93,7 @@ machine_args_cavium =3D [ >>>=20 >>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >>> machine_args_generic] >>> -impl_0x41 =3D ['Arm', flags_generic, machine_args_generic] >>> +impl_0x41 =3D ['Arm', flags_arm, machine_args_generic] >>> impl_0x42 =3D ['Broadcom', flags_generic, machine_args_generic] >>> impl_0x43 =3D ['Cavium', flags_cavium, machine_args_cavium] >>> impl_0x44 =3D ['DEC', flags_generic, machine_args_generic] >>> -- >>> 2.11.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 98D2AA00E6 for ; Thu, 18 Apr 2019 13:32:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EB28A1B950; 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Thu, 18 Apr 2019 11:32:32 +0000 From: Yongseok Koh To: Hemant Agrawal , Honnappa Nagarahalli CC: "bruce.richardson@intel.com" , "jerinj@marvell.com" , "pbhagavatula@marvell.com" , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "Gavin Hu (Arm Technology China)" , nd Thread-Topic: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache line size for armv8 Thread-Index: AQHU9cATrNlj8cLQjUildp2P3jR4HKZByVGA Date: Thu, 18 Apr 2019 11:32:32 +0000 Message-ID: <62E7B12F-C840-454E-B7E7-9DA9734384C0@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190418014726.20600-1-yskoh@mellanox.com> <20190418014726.20600-2-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f4f57ba3-5468-41c4-ed60-08d6c3f18c59 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ZSRnmPPF9RdDNbzIL97XnNntPwl4XVJI948MQTY7gDj0kfSISuRpxt47APEakba4aBvqH8RdmLP79cB6CdqmQ1ATcB0TuKISBfh7uiAkVSN4ZiSBzXwgkvVH2D9LMFjP1DD/d4Q4xSdOUjERMiiF1ISGtj1vRJgH4ocF9NUTSDkS2u1WRuR6Ie55rdfWRfQ0HknzMShDTZkZ/PATGhfOn6sUpZ+Jbqdb28/5efFGR755PbaJLyXaVx72zp8SJU2t4vhU0W/qN98hrgv1XYpRQ3XFfR8OlmPkQEC1wuYTNKo8UGnHqW/KgLooSAYgIUetMWR1yve4cV5uQ9uEmd79nAAbvaqzNhT3Tqq8hKcxtgGT9npW/mRw4P3ibkCjTep2EV8Sg6VahlMjDGkAE5TEGCl0sdJwU5ZKcb6iWxTjp+Q= Content-Type: text/plain; charset="UTF-8" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4f57ba3-5468-41c4-ed60-08d6c3f18c59 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Apr 2019 11:32:32.7081 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB3810 Subject: Re: [dpdk-dev] [EXT] Re: [PATCH v2 2/4] meson: change default cache line size for armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190418113232.YLDybWR3Fqzxyv43wRVa--R7vLHerFY92_2YtnjQM2I@z> > On Apr 18, 2019, at 1:23 AM, Hemant Agrawal wrot= e: >=20 >> -----Original Message----- >> From: dev On Behalf Of Honnappa Nagarahalli >> Sent: Thursday, April 18, 2019 10:31 AM >> To: yskoh@mellanox.com; bruce.richardson@intel.com; jerinj@marvell.com; >> pbhagavatula@marvell.com; shahafs@mellanox.com >> Cc: dev@dpdk.org; thomas@monjalon.net; Gavin Hu (Arm Technology >> China) ; Honnappa Nagarahalli >> ; nd ; nd >> Subject: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache >> line size for armv8 >>=20 >=20 >>>=20 >>> Currently, the cache line size of armv8 CPUs having Implementor ID of >>> 0x41 is >>> 64 bytes. >> I guess you meant to say 128 bytes >=20 >=20 > "the current default is 128, changing it to 64." Yep, the message was wrong. Will fix it. >>> Signed-off-by: Yongseok Koh >>> --- >>>=20 >>> v2: >>> * introduce flags_arm replacing flags_generic instead of using the >>> extra flags >>>=20 >>> config/arm/meson.build | 7 ++++++- >>> 1 file changed, 6 insertions(+), 1 deletion(-) >>>=20 >>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>> 22a062bad9..1db4ad2ee7 100644 >>> --- a/config/arm/meson.build >>> +++ b/config/arm/meson.build >>> @@ -32,6 +32,11 @@ flags_generic =3D [ >>> ['RTE_MAX_LCORE', 256], >>> ['RTE_USE_C11_MEM_MODEL', true], >>> ['RTE_CACHE_LINE_SIZE', 128]] >>> +flags_arm =3D [ >>> + ['RTE_MACHINE', '"armv8a"'], >>> + ['RTE_MAX_LCORE', 256], >> I am not aware of any implementations with implementor ID 0x41. Bluefiel= d >> is the first one I am aware of. May be we can keep this smaller, 16? >=20 > NXP also support implementer as 0x41, 16 will be good.=20 BlueField has 16 cores so yes, it is good. Thanks, Yongseok >=20 >>=20 >>> + ['RTE_USE_C11_MEM_MODEL', true], >>> + ['RTE_CACHE_LINE_SIZE', 64]] >>> flags_cavium =3D [ >>> ['RTE_CACHE_LINE_SIZE', 128], >>> ['RTE_MAX_NUMA_NODES', 2], >>> @@ -88,7 +93,7 @@ machine_args_cavium =3D [ >>>=20 >>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >>> machine_args_generic] >>> -impl_0x41 =3D ['Arm', flags_generic, machine_args_generic] >>> +impl_0x41 =3D ['Arm', flags_arm, machine_args_generic] >>> impl_0x42 =3D ['Broadcom', flags_generic, machine_args_generic] >>> impl_0x43 =3D ['Cavium', flags_cavium, machine_args_cavium] >>> impl_0x44 =3D ['DEC', flags_generic, machine_args_generic] >>> -- >>> 2.11.0