From: Thomas Monjalon <thomas@monjalon.net>
To: David Christensen <drc@linux.vnet.ibm.com>
Cc: dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
Date: Thu, 02 May 2019 23:45:06 +0200 [thread overview]
Message-ID: <6327337.9PMvuZf6XJ@xps> (raw)
In-Reply-To: <1556663603-39934-1-git-send-email-drc@linux.vnet.ibm.com>
Hi,
01/05/2019 00:33, David Christensen:
> The memory barrier test fails on IBM Power 9 systems. Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
>
> Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
[...]
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -36,7 +36,7 @@
> #include "test.h"
>
> #define ADD_MAX 8
> -#define ITER_MAX 0x100000000
> +#define ITER_MAX 0x1000000
This is a revert of a change done in patch 3.
> @@ -92,12 +92,19 @@ struct lcore_plock_test {
> other = self ^ 1;
>
> l->flag[self] = 1;
> +#ifdef RTE_ARCH_PPC_64
> + rte_smp_wmb();
> +#endif
You should not have such #ifdef in a test case
supposed to run on all architectures with the same code.
What can be fixed in EAL?
next prev parent reply other threads:[~2019-05-02 21:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-30 22:33 David Christensen
2019-04-30 22:33 ` David Christensen
2019-05-02 21:45 ` Thomas Monjalon [this message]
2019-05-02 21:45 ` Thomas Monjalon
2019-05-06 18:26 ` David Christensen
2019-05-06 18:26 ` David Christensen
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