From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C91D0A2EDB for ; Sun, 29 Sep 2019 10:55:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 145181F28; Sun, 29 Sep 2019 10:55:48 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 930A8DE3 for ; Sun, 29 Sep 2019 10:55:46 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Sep 2019 01:55:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,562,1559545200"; d="scan'208";a="193836108" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 29 Sep 2019 01:55:44 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 29 Sep 2019 01:55:44 -0700 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 29 Sep 2019 01:55:44 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.166]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.225]) with mapi id 14.03.0439.000; Sun, 29 Sep 2019 16:55:42 +0800 From: "Su, Simei" To: "Zhang, Qi Z" , "Wu, Jingjing" , "Ye, Xiaolong" , "Yigit, Ferruh" CC: "dev@dpdk.org" Thread-Topic: [PATCH v7 2/3] ethdev: extend RSS offload types Thread-Index: AQHVdpTYXO8P58DCf0uoQJVM7Socx6dCWW9Q Date: Sun, 29 Sep 2019 08:55:41 +0000 Message-ID: <65F28F834D25B54B9EC1999B623071B30C45F3EE@SHSMSX104.ccr.corp.intel.com> References: <1569733870-333768-1-git-send-email-simei.su@intel.com> <1569740956-69634-1-git-send-email-simei.su@intel.com> <1569740956-69634-3-git-send-email-simei.su@intel.com> In-Reply-To: <1569740956-69634-3-git-send-email-simei.su@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjE0NDUyYWYtYzI0YS00Y2JjLWE3ODYtYWY1ZDQ1NDIxODc2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoia29kQ0tDVkF0OTNreHAzU0hUUDIzSXpYVGtcLzUwVHdFWUJMZWYrZHVcLzcyUUxsR3F6b1lNVmhha29KdkUxbXFrIn0= x-ctpclassification: CTP_NT x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v7 2/3] ethdev: extend RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Su, Simei > Sent: Sunday, September 29, 2019 3:09 PM > To: Zhang, Qi Z ; Wu, Jingjing ; > Ye, Xiaolong ; Yigit, Ferruh > Cc: dev@dpdk.org; Su, Simei > Subject: [PATCH v7 2/3] ethdev: extend RSS offload types >=20 > This patch reserves several bits as input set selection from the high end= of the 64 > bits. It is combined with exisiting ETH_RSS_* to represent rss types. >=20 > for example: > ETH_RSS_IPV4 | ETH_RSS_L3_SRC_ONLY: hash on src ip address only > ETH_RSS_IPV4_UDP | ETH_RSS_L4_DST_ONLY: hash on src/dst IP and > dst UDP port >=20 > Signed-off-by: Simei Su Acked-by: Ori Kam > --- > lib/librte_ethdev/rte_ethdev.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) >=20 > diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethde= v.h index > 7722f70..e68bca8 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -505,6 +505,19 @@ struct rte_eth_rss_conf { > #define ETH_RSS_GENEVE (1ULL << 20) > #define ETH_RSS_NVGRE (1ULL << 21) >=20 > +/* > + * We use the following macros to combine with above ETH_RSS_* for > + * more specific input set selection. These bits are defined starting > + * from the high end of the 64 bits. > + * Note: If we use above ETH_RSS_* without SRC/DST_ONLY, it represents > + * both SRC and DST are taken into account. SRC_ONLY and DST_ONLY of > + * the same level can't be used simultaneously. > + */ > +#define ETH_RSS_L3_SRC_ONLY (1ULL << 63) > +#define ETH_RSS_L3_DST_ONLY (1ULL << 62) > +#define ETH_RSS_L4_SRC_ONLY (1ULL << 61) > +#define ETH_RSS_L4_DST_ONLY (1ULL << 60) > + > #define ETH_RSS_IP ( \ > ETH_RSS_IPV4 | \ > ETH_RSS_FRAG_IPV4 | \ > -- > 1.8.3.1