From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 918462B9D for ; Thu, 2 Mar 2017 02:22:30 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP; 01 Mar 2017 17:22:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,228,1484035200"; d="scan'208";a="939617506" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga003.jf.intel.com with ESMTP; 01 Mar 2017 17:22:28 -0800 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 1 Mar 2017 17:22:28 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 1 Mar 2017 17:22:27 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX103.ccr.corp.intel.com ([10.239.4.69]) with mapi id 14.03.0248.002; Thu, 2 Mar 2017 09:22:25 +0800 From: "Lu, Wenzhuo" To: Olivier Matz , "dev@dpdk.org" , "thomas.monjalon@6wind.com" , "Ananyev, Konstantin" , "Zhang, Helin" , "Wu, Jingjing" , "adrien.mazarguil@6wind.com" , "nelio.laranjeiro@6wind.com" CC: "Yigit, Ferruh" , "Richardson, Bruce" Thread-Topic: [PATCH 4/6] net/e1000: implement descriptor status API (em) Thread-Index: AQHSkrAXA56qFbnafEKEESP24bxhvKGAwAsQ Date: Thu, 2 Mar 2017 01:22:25 +0000 Message-ID: <6A0DE07E22DDAD4C9103DF62FEBC09093B569F66@shsmsx102.ccr.corp.intel.com> References: <1479981261-19512-1-git-send-email-olivier.matz@6wind.com> <1488388752-1819-1-git-send-email-olivier.matz@6wind.com> <1488388752-1819-5-git-send-email-olivier.matz@6wind.com> In-Reply-To: <1488388752-1819-5-git-send-email-olivier.matz@6wind.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 4/6] net/e1000: implement descriptor status API (em) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Mar 2017 01:22:31 -0000 Hi Oliver, > -----Original Message----- > From: Olivier Matz [mailto:olivier.matz@6wind.com] > Sent: Thursday, March 2, 2017 1:19 AM > To: dev@dpdk.org; thomas.monjalon@6wind.com; Ananyev, Konstantin; Lu, > Wenzhuo; Zhang, Helin; Wu, Jingjing; adrien.mazarguil@6wind.com; > nelio.laranjeiro@6wind.com > Cc: Yigit, Ferruh; Richardson, Bruce > Subject: [PATCH 4/6] net/e1000: implement descriptor status API (em) >=20 > Signed-off-by: Olivier Matz > +int > +eth_em_tx_descriptor_status(struct rte_eth_dev *dev, uint16_t tx_queue_i= d, > + uint16_t offset) > +{ > + volatile uint8_t *status; > + struct em_tx_queue *txq; > + uint32_t desc; > + > + txq =3D dev->data->tx_queues[tx_queue_id]; > + if (unlikely(offset >=3D txq->nb_tx_desc)) > + return -EINVAL; > + > + desc =3D txq->tx_tail + offset; > + /* go to next desc that has the RS bit */ > + desc =3D ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * > + txq->tx_rs_thresh; The descriptor may be changed here. So the return value may not be for the = offset one. Why? > + status =3D &txq->tx_ring[desc].upper.fields.status; > + if (*status & E1000_TXD_STAT_DD) > + return RTE_ETH_TX_DESC_DONE; > + > + return RTE_ETH_TX_DESC_FULL; > +} > + > void > em_dev_clear_queues(struct rte_eth_dev *dev) { > -- > 2.8.1