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From: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
To: "Min Hu (Connor)" <humin29@huawei.com>, dev@dpdk.org
Cc: ferruh.yigit@intel.com, Stephen Hemminger <sthemmin@microsoft.com>
Subject: Re: [dpdk-dev] [PATCH v2] net/hns3: support Tx push quick doorbell to improve perf
Date: Thu, 17 Jun 2021 18:18:39 +0300	[thread overview]
Message-ID: <6a9b27c2-1bab-e2a2-a6e6-c1e4300505c4@oktetlabs.ru> (raw)
In-Reply-To: <1623720869-26320-1-git-send-email-humin29@huawei.com>

On 6/15/21 4:34 AM, Min Hu (Connor) wrote:
> From: Chengwen Feng <fengchengwen@huawei.com>
> 
> Kunpeng 930 support Tx push mode which could improve performance, It
> works like below:
> 1. Add PCIe bar45 which support driver direct write the Tx descriptor
> or tail reg to it.
> 2. Support three operations: a) direct write one Tx descriptor, b)
> direct write two Tx descriptors, c) direct write tail reg.
> 3. The original tail reg located at bar23, the above bar45 tail reg
> could provide better bandwidth from the hardware perspective.
> 
> The hns3 driver only support direct write tail reg (also have the name
> of quick doorbell), the detail:
> Considering compatibility, firmware will report Tx push capa if the
> hardware support it.
> 
> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>

With description mangled a bit and few minor fixes
described below.

Applied, thanks.

[snip]

> diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
> index 1d7a769..1fb16cd 100644
> --- a/drivers/net/hns3/hns3_rxtx.c
> +++ b/drivers/net/hns3/hns3_rxtx.c
> @@ -2892,6 +2892,69 @@ hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf,
>  	return 0;
>  }
>  
> +static void *
> +hns3_tx_push_get_queue_tail_reg(struct rte_eth_dev *dev, uint16_t queue_id)
> +{
> +#define HNS3_TX_PUSH_TQP_REGION_SIZE		0x10000
> +#define HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET	64
> +#define HNS3_TX_PUSH_PCI_BAR_INDEX		4
> +
> +	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
> +	uint8_t bar_id = HNS3_TX_PUSH_PCI_BAR_INDEX;
> +
> +	/*
> +	 * If device support Tx push then its PCIe bar45 must exist, and DPDK
> +	 * framework will mmap the bar45 default in pci probe stage.

pci -> PCI

> +	 *
> +	 * In the bar45, the first half is for roce(RDMA over Converged

roce -> RoCE

> +	 * Ethernet), and the second half is for NIC, every TQP occupy 64KB.
> +	 *
> +	 * The quick doorbell located at 64B offset in the TQP region.
> +	 */
> +	return (void *)((char *)pci_dev->mem_resource[bar_id].addr +
> +			(pci_dev->mem_resource[bar_id].len >> 1) +
> +			HNS3_TX_PUSH_TQP_REGION_SIZE * queue_id +
> +			HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET);

Remove unnecessary type cast to 'void *'.

[snip]

      parent reply	other threads:[~2021-06-17 15:18 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-13  1:42 [dpdk-dev] [PATCH] " Min Hu (Connor)
2021-06-13  1:42 ` Min Hu (Connor)
2021-06-14 14:35   ` Andrew Rybchenko
2021-06-15  1:35     ` Min Hu (Connor)
2021-06-15  1:34   ` [dpdk-dev] [PATCH v2] " Min Hu (Connor)
2021-06-15  2:36     ` Stephen Hemminger
2021-06-15  2:37     ` Stephen Hemminger
2021-06-15  3:46       ` Min Hu (Connor)
2021-06-17 15:18     ` Andrew Rybchenko [this message]

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