From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E8CC41F50; Wed, 12 Jun 2024 17:20:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA1C142F9F; Wed, 12 Jun 2024 17:06:16 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 02AB942F85 for ; Wed, 12 Jun 2024 17:06:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204774; x=1749740774; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aKnZfj+DkdvSymZI77OrcdbZqmDSnwKykGo1SIDiqJg=; b=WLG+Uo6iM3dZc/Crf6+o0+VMj0zcBUaeDP8LyMEpJxZ0zJ75jzyEgb+g tULMIgOpnEk029syZsXOf6FK5WfCkXDwwoE4TFtzZql4DIAhihyJ89UFz z2QfctX/tTakyliPmRh4f/zf8tfXUMK5qi1nh8Z7qCnbq4KfqtHXp7vM2 lFk+WBFl405+hJPTXyK1mSQdrZSRftVD7p2USCR2XB52uNedD+iysfhTB C4VjKL5T430lY2EnDbFL81OV2kDshmTtnaQhatP3JAvOwNbMQSCg4gE62 jB6JFn06QBBLIxntk69/8D0qosyUC5YcS1INn7HXr8YYHiRsW6Y4BmdiS g==; X-CSE-ConnectionGUID: VNN647sCRz+uz2P3Ei1Gqg== X-CSE-MsgGUID: S0WOZ5dWQaKOgT21IbAf4A== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459898" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459898" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:06:14 -0700 X-CSE-ConnectionGUID: /zVu2k5YQuK1MrldU7pwqw== X-CSE-MsgGUID: 1FYykSejTaKU2DLkw3wciQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925842" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:06:12 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Jacob Keller Subject: [PATCH v2 107/148] net/ice/base: return high address for multi-read eth56g registers Date: Wed, 12 Jun 2024 16:01:41 +0100 Message-ID: <6b88985c23ed25891882c52f4b67c2b56d372e43.1718204529.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes The eth56g register checks for 40b and 64b registers do not return the high address offset. Instead it is expected that all offsets are exactly 4 bytes apart in the expected order. The e822 implementations explicitly return the address in the lookup function. This form is better because it allows for the potential of registers which may not have a static offset. Match the e822 style by refactoring these functions to return the high address in a function parameter. Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 43 ++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 72a11a7e39..938707afdf 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1209,19 +1209,35 @@ ice_phy_port_mem_write_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val) /** * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register * @low_addr: the low address to check + * @high_addr: on return, contains the high address of the 64bit register * * Checks if the provided low address is one of the known 64bit PHY values - * represented as two 32bit registers. + * represented as two 32bit registers. If it is, return the appropriate high + * register offset to use. */ -static bool ice_is_64b_phy_reg_eth56g(u16 low_addr) +static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) { switch (low_addr) { case PHY_REG_TX_TIMER_INC_PRE_L: + *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; + return true; case PHY_REG_RX_TIMER_INC_PRE_L: + *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; + return true; case PHY_REG_TX_CAPTURE_L: + *high_addr = PHY_REG_TX_CAPTURE_U; + return true; case PHY_REG_RX_CAPTURE_L: + *high_addr = PHY_REG_RX_CAPTURE_U; + return true; case PHY_REG_TOTAL_TX_OFFSET_L: + *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; + return true; case PHY_REG_TOTAL_RX_OFFSET_L: + *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; + return true; + case PHY_REG_TX_MEMORY_STATUS_L: + *high_addr = PHY_REG_TX_MEMORY_STATUS_U; return true; default: return false; @@ -1231,15 +1247,18 @@ static bool ice_is_64b_phy_reg_eth56g(u16 low_addr) /** * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register * @low_addr: the low address to check + * @high_addr: on return, contains the high address of the 40bit value * * Checks if the provided low address is one of the known 40bit PHY values * split into two registers with the lower 8 bits in the low register and the - * upper 32 bits in the high register. + * upper 32 bits in the high register. If it is, return the high register + * offset to use. */ -static bool ice_is_40b_phy_reg_eth56g(u16 low_addr) +static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) { switch (low_addr) { case PHY_REG_TIMETUS_L: + *high_addr = PHY_REG_TIMETUS_U; return true; default: return false; @@ -1261,11 +1280,11 @@ static bool ice_is_40b_phy_reg_eth56g(u16 low_addr) static int ice_read_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) { - u16 high_addr = low_addr + sizeof(u32); int err; + u16 high_addr; u32 lo, hi; - if (!ice_is_40b_phy_reg_eth56g(low_addr)) + if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) return ICE_ERR_PARAM; err = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo); @@ -1302,11 +1321,11 @@ ice_read_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) { - u16 high_addr = low_addr + sizeof(u32); int err; + u16 high_addr; u32 lo, hi; - if (!ice_is_64b_phy_reg_eth56g(low_addr)) + if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) return ICE_ERR_PARAM; err = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo); @@ -1343,11 +1362,11 @@ ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) { - u16 high_addr = low_addr + sizeof(u32); int err; + u16 high_addr; u32 lo, hi; - if (!ice_is_40b_phy_reg_eth56g(low_addr)) + if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) return ICE_ERR_PARAM; lo = (u32)(val & P_REG_40B_LOW_M); @@ -1384,11 +1403,11 @@ ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) { - u16 high_addr = low_addr + sizeof(u32); int err; + u16 high_addr; u32 lo, hi; - if (!ice_is_64b_phy_reg_eth56g(low_addr)) + if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) return ICE_ERR_PARAM; lo = ICE_LO_DWORD(val); -- 2.43.0