From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 1605E592C for ; Thu, 12 Jan 2017 20:09:59 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 12 Jan 2017 11:09:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,219,1477983600"; d="scan'208";a="29643581" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.237.220.38]) ([10.237.220.38]) by orsmga002.jf.intel.com with ESMTP; 12 Jan 2017 11:09:23 -0800 To: Jerin Jacob , dev@dpdk.org References: <1482832175-27199-1-git-send-email-jerin.jacob@caviumnetworks.com> <1484212646-10338-1-git-send-email-jerin.jacob@caviumnetworks.com> <1484212646-10338-16-git-send-email-jerin.jacob@caviumnetworks.com> Cc: konstantin.ananyev@intel.com, thomas.monjalon@6wind.com, bruce.richardson@intel.com, jianbo.liu@linaro.org, viktorin@rehivetech.com, santosh.shukla@caviumnetworks.com, John Griffin , Fiona Trahe , Deepak Kumar Jain From: Ferruh Yigit Message-ID: <6bb9980b-f546-38d5-044a-63507510f6a5@intel.com> Date: Thu, 12 Jan 2017 19:09:22 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <1484212646-10338-16-git-send-email-jerin.jacob@caviumnetworks.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v3 15/29] crypto/qat: use eal I/O device memory read/write API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2017 19:10:00 -0000 Hi Jerin, On 1/12/2017 9:17 AM, Jerin Jacob wrote: <...> > +#include > + > /* CSR write macro */ > -#define ADF_CSR_WR(csrAddr, csrOffset, val) \ > - (void)((*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)) \ > - = (val))) > +#define ADF_CSR_WR(csrAddr, csrOffset, val) \ > + rte_write32(val, (((uint8_t *)csrAddr) + csrOffset)) For IA, this update introduces an extra compiler barrier (rte_io_wmb()), which is indeed not a must, is this correct? If so, does it make sense to override these functions for x86, and make rte_writeX = rte_writeX_relaxed rte_readX = rte_readX_relaxed > > /* CSR read macro */ > -#define ADF_CSR_RD(csrAddr, csrOffset) \ > - (*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset))) > +#define ADF_CSR_RD(csrAddr, csrOffset) \ > + rte_read32((((uint8_t *)csrAddr) + csrOffset)) This patchset both introduces new rte_readX/rte_writeX functions, also applies them into drivers. While applying them, it changes the behavior. Like above code was doing a read, but after update it does read and read_memory_barrier. What do you think this patchset updates usage in a manner that keeps behavior exact same. Like using rte_read32_relaxed for this case. And doing architecture related updates in a different patchset? This both makes easy to see architecture specific updates, and makes easy to trace any possible performance issues by this patchset. > > #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL > #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL >