From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f51.google.com (mail-wm0-f51.google.com [74.125.82.51]) by dpdk.org (Postfix) with ESMTP id 8F02A29CA for ; Tue, 4 Oct 2016 10:46:57 +0200 (CEST) Received: by mail-wm0-f51.google.com with SMTP id b201so130272855wmb.0 for ; Tue, 04 Oct 2016 01:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:user-agent:in-reply-to :references:mime-version:content-transfer-encoding; bh=A63dMHHThigNkHvL0NcGbkJsZCLzkBOoee6m81Hateo=; b=MlHf2IYONgRIVcbl9NUPEgJJuGDBhOV5NN4MEEDx+fnJ5G8ecCHEguiQCWzchpEY28 dPAdZqAkIehD36CqNLpIp5MByail5ZPfoG/n012Zph/iLvQr4UhDT0oCMLbNRFVdp7yb d9r7XB0F2JdxOBdRfYyByOULdEJOMnKQRlOybd52hGmrm11SvT+B8xoyWdVRxHdRYdZr 0W3IeejQKLVVhiSex3ecI/GMDWFbHhqbriRj9naM3/Pj0Mo7Wg0D6t6LaaXF+KmMN9JH CGrwSoZNukQHYCWxuMUJ/F91CsGwnFBy7azGvmiEE5XiKizULAzq/ZIxoBW+NaIWd1Aq Imtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:user-agent :in-reply-to:references:mime-version:content-transfer-encoding; bh=A63dMHHThigNkHvL0NcGbkJsZCLzkBOoee6m81Hateo=; b=YIIUuYhB1sIY7NuhG844kFwrTRy1GMhEHU30Dr/aMcCFgtYlTntAHCjqHx5l5JNEsN Xa4PqYfUBgCGuuECZkRdK5MUYE0xObVUE6+RdryARvlExtzT1WDc3HEiBs6Uz+thoCqR stBAk70Ew/u02scuL/ygiMY9M36WTujB6Tkvapeo/JRQqHcGHZ/sPX+3XsYBNdZ3cSyi e1FPN83r0tMkNqZgjpjvtfqtLeY8WzTObztR+VXtIxcNC0uvcW0kwg4PlpGygnobFe0S xl4wAyoUx63MD5OJRpTj54yK8Ei3nuLmxQZ5amWfFsQg7seo9fWrT9tIb/5DZdKAYltd /+FQ== X-Gm-Message-State: AA6/9RmAJKyPLpSX/2fE98Rl1hUe8OG4PZdIjcCJwBMMZcuL+thfELzfFIKCI9oUW/R/O6x8 X-Received: by 10.28.142.197 with SMTP id q188mr2681920wmd.119.1475570817356; Tue, 04 Oct 2016 01:46:57 -0700 (PDT) Received: from xps13.localnet (172.17.90.92.rev.sfr.net. [92.90.17.172]) by smtp.gmail.com with ESMTPSA id j198sm2912241wmg.4.2016.10.04.01.46.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Oct 2016 01:46:56 -0700 (PDT) From: Thomas Monjalon To: Jerin Jacob Cc: Hemant Agrawal , dev@dpdk.org, "jianbo.liu@linaro.org" , "viktorin@rehivetech.com" Date: Tue, 04 Oct 2016 10:46:54 +0200 Message-ID: <7060882.CcMXuoxNGC@xps13> User-Agent: KMail/4.14.10 (Linux/4.5.4-1-ARCH; KDE/4.14.11; x86_64; ; ) In-Reply-To: References: <1471521090-21067-1-git-send-email-jerin.jacob@caviumnetworks.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] eal/armv8: high-resolution cycle counter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Oct 2016 08:46:57 -0000 > > Existing cntvct_el0 based rte_rdtsc() provides portable means to get wall clock > > counter at user space. Typically it runs at <= 100MHz. > > > > The alternative method to enable rte_rdtsc() for high resolution wall clock > > counter is through armv8 PMU subsystem. > > The PMU cycle counter runs at CPU frequency, However, access to PMU cycle > > counter from user space is not enabled by default in the arm64 linux kernel. > > It is possible to enable cycle counter at user space access by configuring the > > PMU from the privileged mode (kernel space). > > > > by default rte_rdtsc() implementation uses portable > > cntvct_el0 scheme. Application can choose the PMU based implementation with > > CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU > > > > Signed-off-by: Jerin Jacob > > Acked-by: Hemant Agrawal Applied, thanks Please do not forget documentation and upstreaming efforts.