From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail1.windriver.com (mail1.windriver.com [147.11.146.13]) by dpdk.org (Postfix) with ESMTP id 423F34CC5 for ; Wed, 5 Apr 2017 22:23:37 +0200 (CEST) Received: from ALA-HCA.corp.ad.wrs.com (ala-hca.corp.ad.wrs.com [147.11.189.40]) by mail1.windriver.com (8.15.2/8.15.1) with ESMTPS id v35KNa0p003264 (version=TLSv1 cipher=AES128-SHA bits=128 verify=FAIL); Wed, 5 Apr 2017 13:23:36 -0700 (PDT) Received: from ALA-MBC.corp.ad.wrs.com ([fe80::fcbe:9b7:1141:89a1]) by ALA-HCA.corp.ad.wrs.com ([147.11.189.40]) with mapi id 14.03.0294.000; Wed, 5 Apr 2017 13:23:36 -0700 From: "Legacy, Allain" To: "Nelio Laranjeiro (nelio.laranjeiro@6wind.com)" , "Adrien Mazarguil (adrien.mazarguil@6wind.com)" CC: "dev@dpdk.org" Thread-Topic: mlx5 vxlan match filter vni endianness Thread-Index: AdKuSlw7OIfKgrmsS+abSVgguVZ6Pg== Date: Wed, 5 Apr 2017 20:23:35 +0000 Message-ID: <70A7408C6E1BFB41B192A929744D852396902508@ALA-MBC.corp.ad.wrs.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [128.224.140.166] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: [dpdk-dev] mlx5 vxlan match filter vni endianness X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Apr 2017 20:23:42 -0000 Hi, None of the comments in the rte_flow.h file (or the programmers guide) spec= ify what endianness should be applied to spec/mask fields. Based on the te= sting I have done so far using a CX4 device (mlx5 driver) fields like VLAN = ID and UDP ports are expected in network byte order. There seems to be a d= iscrepancy with how VXLAN VNI values are expected; at least for this one dr= iver. Matching only works on VNI if it is specified in host byte order. /** * RTE_FLOW_ITEM_TYPE_VXLAN. * * Matches a VXLAN header (RFC 7348). */ struct rte_flow_item_vxlan { uint8_t flags; /**< Normally 0x08 (I flag). */ uint8_t rsvd0[3]; /**< Reserved, normally 0x000000. */ uint8_t vni[3]; /**< VXLAN identifier. */ uint8_t rsvd1; /**< Reserved, normally 0x00. */ }; I have not done any testing on an i40e device yet, but looking at the i40e_= flow.c code it looks like that driver expects to receive the VNI in network= byte order: if (vxlan_spec && vxlan_mask && !is_vni_mas= ked) { /* If there's vxlan */ rte_memcpy(((uint8_t *)&ten= ant_id_be + 1), vxlan_sp= ec->vni, 3); filter->tenant_id =3D rte_b= e_to_cpu_32(tenant_id_be); if (!o_eth_spec && !o_eth_m= ask && Can you confirm whether the mlx5_flow.c behavior is a bug or whether my und= erstand is incorrect? Regards, Allain Allain Legacy, Software Developer, Wind River direct 613.270.2279=A0=A0fax 613.492.7870 skype allain.legacy 350 Terry Fox Drive, Suite 200, Ottawa, Ontario, K2K 2W5 =A0