From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 86AB7454EF; Tue, 25 Jun 2024 13:30:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E04E4337B; Tue, 25 Jun 2024 13:20:52 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 3303142F0C for ; Tue, 25 Jun 2024 13:18:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314295; x=1750850295; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WYfikIkwevKuuoJnw+hceVuH5738tq18VYhlsbO8NPc=; b=TRt1jQVaSPZgpg6ZEV1b0gN+ww3s8EXuUiQmAQyjCNVSThnP4jxbT+h8 KBOgqQ7Jw3fIHY9q4yaqdqrwYd2FS4cYjJyGsksDni9QEQRuwcHIOER97 EA/ZWCKLioQk7BjySmNccpA/vH9LgpK972nqXtBssEbtqVpLl9zIm7x3P IJlTgbGYQ7ANU9vTP6eziN16cMP1HAnLmgsJ3ckpl5G7MX+lWYDUvGGS3 HN3gzI0F76irmzZHwqgAh4QJVMy3op8GgpvT+tBlweUXsUH/G7znEOiNk Uo+SFopM0XGfufF+KKDOF7//kS15aMOPevWxvU2DHQO0ZQR+p0BqHDsqW g==; X-CSE-ConnectionGUID: icrXDX7KRuyRtADe/8g7XA== X-CSE-MsgGUID: FjHfcionRQKVcPenONCF5g== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080665" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080665" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:18:14 -0700 X-CSE-ConnectionGUID: BA1GkuQsT1iBzrSsonaE1w== X-CSE-MsgGUID: c6vx3wVFRi++ucahGhuygQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719787" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:14 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Karol Kolacinski , bruce.richardson@intel.com, ian.stokes@intel.com, Jacob Keller Subject: [PATCH v3 121/129] net/ice/base: cleanup timestamp registers correctly Date: Tue, 25 Jun 2024 12:14:06 +0100 Message-ID: <70c9e25392a45f7c7dafb4d3d4bdc472a30f702f.1719313664.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Karol Kolacinski E822 PHY TS registers should not be written and the only way to cleanup them is to reset QUAD memory. To ensure that the status bit for the timestamp index is cleared, ensure that ice_clear_phy_tstamp implementations first read the timestamp out. Implementations which can write the register continue to do so. Add a note to indicate this function should only be called on timestamps which have their valid bit set. Signed-off-by: Karol Kolacinski Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 63 +++++++++++++++++-------------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 9913cb76fe..70f3b2d3d1 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1554,8 +1554,18 @@ static int ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) { int err; + u64 unused_tstamp; u16 lo_addr; + /* Read the timestamp register to ensure the timestamp status bit is + * cleared. + */ + err = ice_read_phy_tstamp_eth56g(hw, port, idx, &unused_tstamp); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", + port, idx, err); + } + lo_addr = (u16)PHY_TSTAMP_L(idx); err = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0); @@ -2955,25 +2965,16 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) * This function should only be called on an idx whose bit is set according to * ice_get_phy_tx_tstamp_ready(). */ -static int ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) +static int +ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) { + u64 unused_tstamp; int err; - u16 lo_addr, hi_addr; - lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); - hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); - - err = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", - err); - return err; - } - - err = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); + err = ice_read_phy_tstamp_e822(hw, quad, idx, &unused_tstamp); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", + quad, idx, err); return err; } @@ -4884,40 +4885,44 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) } /** - * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block + * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY * @hw: pointer to the HW struct * @lport: the lport to read from * @idx: the timestamp index to reset * - * Clear a timestamp from the timestamp block, discarding its value without - * returning it. This resets the memory status bit for the timestamp index - * allowing it to be reused for another timestamp in the future. + * Read the timestamp and then forcibly overwrite its value to clear the valid + * bit from the timestamp block of the external PHY on the E810 device. * - * For E822 devices, the block number is the PHY quad to clear from. For E810 - * devices, the block number is the logical port to clear from. - * - * This function must only be called on a timestamp index whose valid bit is - * set according to ice_get_phy_tx_tstamp_ready(). + * This function should only be called on an idx whose bit is set according to + * ice_get_phy_tx_tstamp_ready(). */ static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) { - int err; u32 lo_addr, hi_addr; + u64 unused_tstamp; + int err; + + err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); + return err; + } lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); err = ice_write_phy_reg_e810(hw, lo_addr, 0); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); return err; } err = ice_write_phy_reg_e810(hw, hi_addr, 0); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); return err; } -- 2.43.0