From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 645AAA0C4D; Mon, 6 Sep 2021 02:21:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CF3D040A4B; Mon, 6 Sep 2021 02:21:08 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 3464C40042 for ; Mon, 6 Sep 2021 02:21:07 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10098"; a="280862249" X-IronPort-AV: E=Sophos;i="5.85,271,1624345200"; d="scan'208";a="280862249" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2021 17:21:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,271,1624345200"; d="scan'208";a="604379309" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by fmsmga001.fm.intel.com with ESMTP; 05 Sep 2021 17:21:05 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Sun, 5 Sep 2021 17:21:05 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Mon, 6 Sep 2021 08:21:03 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.012; Mon, 6 Sep 2021 08:21:03 +0800 From: "Zhang, Qi Z" To: "Zhang, Yuying" , "dev@dpdk.org" Thread-Topic: [PATCH v1] net/ice: refine flow priority support in PF Thread-Index: AQHXnWJku9pE/Xp/Q0qrg53kSEiaAquWLnfA Date: Mon, 6 Sep 2021 00:21:02 +0000 Message-ID: <71152753d48c45ec85be15728b27f3ae@intel.com> References: <20210830052939.2942078-1-yuying.zhang@intel.com> In-Reply-To: <20210830052939.2942078-1-yuying.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] net/ice: refine flow priority support in PF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, Yuying > Sent: Monday, August 30, 2021 1:30 PM > To: dev@dpdk.org; Zhang, Qi Z > Cc: Zhang, Yuying > Subject: [PATCH v1] net/ice: refine flow priority support in PF >=20 > The usage of priority is converse in pipeline mode and non-pipeline mode. > Refine attribute priority support of flow filter in PF driver. When prior= ity is 0, > rules are created in switch filter first and FDIR is used as backup. When= priority > is 1, rules are all created in switch filter. Other filters don't support= priority 1. > Value 0 denotes higher priority. >=20 > Signed-off-by: Yuying Zhang > --- > drivers/net/ice/ice_acl_filter.c | 5 ++++- > drivers/net/ice/ice_fdir_filter.c | 5 ++++- > drivers/net/ice/ice_generic_flow.c | 4 ++-- > drivers/net/ice/ice_hash.c | 5 ++++- > drivers/net/ice/ice_switch_filter.c | 2 +- > 5 files changed, 15 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_acl_filter.c b/drivers/net/ice/ice_acl_f= ilter.c > index 0c15a7036c..614bd44e23 100644 > --- a/drivers/net/ice/ice_acl_filter.c > +++ b/drivers/net/ice/ice_acl_filter.c > @@ -904,7 +904,7 @@ ice_acl_parse(struct ice_adapter *ad, > uint32_t array_len, > const struct rte_flow_item pattern[], > const struct rte_flow_action actions[], > - uint32_t priority __rte_unused, > + uint32_t priority, > void **meta, > struct rte_flow_error *error) > { > @@ -914,6 +914,9 @@ ice_acl_parse(struct ice_adapter *ad, > uint64_t input_set; > int ret; >=20 > + if (priority >=3D 1) > + return -rte_errno; > + > memset(filter, 0, sizeof(*filter)); > item =3D ice_search_pattern_match_item(ad, pattern, array, array_len, > error); > diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir= _filter.c > index 7ba65b9b04..c9f833c5c9 100644 > --- a/drivers/net/ice/ice_fdir_filter.c > +++ b/drivers/net/ice/ice_fdir_filter.c > @@ -2194,7 +2194,7 @@ ice_fdir_parse(struct ice_adapter *ad, > uint32_t array_len, > const struct rte_flow_item pattern[], > const struct rte_flow_action actions[], > - uint32_t priority __rte_unused, > + uint32_t priority, > void **meta, > struct rte_flow_error *error) > { > @@ -2204,6 +2204,9 @@ ice_fdir_parse(struct ice_adapter *ad, > uint64_t input_set; > int ret; >=20 > + if (priority >=3D 1) > + return -rte_errno; > + > memset(filter, 0, sizeof(*filter)); > item =3D ice_search_pattern_match_item(ad, pattern, array, array_len, > error); > diff --git a/drivers/net/ice/ice_generic_flow.c > b/drivers/net/ice/ice_generic_flow.c > index c2fa75f165..1d557a05f4 100644 > --- a/drivers/net/ice/ice_generic_flow.c > +++ b/drivers/net/ice/ice_generic_flow.c > @@ -1923,9 +1923,9 @@ ice_register_parser(struct ice_flow_parser *parser, > } else { > if (parser->engine->type =3D=3D ICE_FLOW_ENGINE_SWITCH || > parser->engine->type =3D=3D ICE_FLOW_ENGINE_HASH) > - TAILQ_INSERT_TAIL(list, parser_node, node); > - else if (parser->engine->type =3D=3D ICE_FLOW_ENGINE_FDIR) > TAILQ_INSERT_HEAD(list, parser_node, node); > + else if (parser->engine->type =3D=3D ICE_FLOW_ENGINE_FDIR) > + TAILQ_INSERT_TAIL(list, parser_node, node); > else if (parser->engine->type =3D=3D ICE_FLOW_ENGINE_ACL) > TAILQ_INSERT_HEAD(list, parser_node, node); > else > diff --git a/drivers/net/ice/ice_hash.c b/drivers/net/ice/ice_hash.c inde= x > 54d14dfcdd..175780c9ff 100644 > --- a/drivers/net/ice/ice_hash.c > +++ b/drivers/net/ice/ice_hash.c > @@ -1034,7 +1034,7 @@ ice_hash_parse_pattern_action(__rte_unused > struct ice_adapter *ad, > uint32_t array_len, > const struct rte_flow_item pattern[], > const struct rte_flow_action actions[], > - uint32_t priority __rte_unused, > + uint32_t priority, > void **meta, > struct rte_flow_error *error) > { > @@ -1043,6 +1043,9 @@ ice_hash_parse_pattern_action(__rte_unused > struct ice_adapter *ad, > struct ice_rss_meta *rss_meta_ptr; > uint64_t phint =3D ICE_PHINT_NONE; >=20 > + if (priority >=3D 1) > + return -rte_errno; > + > rss_meta_ptr =3D rte_zmalloc(NULL, sizeof(*rss_meta_ptr), 0); > if (!rss_meta_ptr) { > rte_flow_error_set(error, EINVAL, > diff --git a/drivers/net/ice/ice_switch_filter.c > b/drivers/net/ice/ice_switch_filter.c > index f222cb9cb0..28f9ae39d5 100644 > --- a/drivers/net/ice/ice_switch_filter.c > +++ b/drivers/net/ice/ice_switch_filter.c > @@ -1651,7 +1651,7 @@ ice_switch_parse_action(struct ice_pf *pf, > rule_info->sw_act.vsi_handle =3D vsi->idx; > rule_info->rx =3D 1; > rule_info->sw_act.src =3D vsi->idx; > - rule_info->priority =3D priority + 5; > + rule_info->priority =3D 6 - priority; I think this is the chance to replace magic number of switch rule priority = with macro, and also add some comment here to explain the calculation.=20 >=20 > return 0; >=20 > -- > 2.25.1