From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41B8245501; Wed, 26 Jun 2024 14:03:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C3D3E433C7; Wed, 26 Jun 2024 13:56:35 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id A322A42E95 for ; Wed, 26 Jun 2024 13:44:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402299; x=1750938299; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/xaYIPlSoGMiHycpaYmWcYFsYy8wkdnfvX/vmTnGxDI=; b=AtSpqUmnMpdXQoYUhe6R+gwJvQiAklaMWVgSGC8uOSym/fs76ffueUqg sWPdlTXH6yg1Agpp52ck5w5X+lp/kybxuEtqvX41AKyd/6247KBaD4/E4 o36tMb+MPQlAtS3tdGDUkbrMIaA6VoHQDvg2TsTZU061l9WV3WlkYQwL+ 8rBWfVMEgEuJSLtaLwXb3mZefBgUzxwLE+6vyljTH1cNo7++DInlCkVqd FEdbs8etHDIJNmFNyIyoe+OVcbTi3Vv5k8PfZYrASoo2IjHSUEB/UYVn4 OQE/Hi5u5rxYPjd9oDwBCxtD5qZzwPjsBKvM+9Il6cmQIdKY920ndunBN A==; X-CSE-ConnectionGUID: ouFiLNwHTkOkfdLGrKBTKA== X-CSE-MsgGUID: DaY/NA/OQpm5qbmvdHBdBw== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979484" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979484" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:44:59 -0700 X-CSE-ConnectionGUID: Cfo052TiR46++XLShFIb+w== X-CSE-MsgGUID: fWTgh1hmSiOye5Xd7TD/Rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874149" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:44:58 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Aviraj CJ , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 071/103] net/ice/base: allow passing flags to sbq command Date: Wed, 26 Jun 2024 12:41:59 +0100 Message-ID: <71947538f1703e2438fdd739bc7cd62d44955565.1719401848.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Aviraj CJ Currently, sending a command to Sideband Queue (SBQ) is done with unconditionally setting `ICE_AQ_FLAG_RD` flag. This patch allows the caller to pass flags to the SBQ command function, and amends all call sites as needed. Signed-off-by: Aviraj CJ Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_common.c | 12 +++++++----- drivers/net/ice/base/ice_common.h | 6 +++--- drivers/net/ice/base/ice_ptp_hw.c | 20 ++++++++++---------- 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index de87df8f60..7b899f0782 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1770,11 +1770,12 @@ ice_sbq_send_cmd_nolock(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, * ice_sbq_rw_reg_lp - Fill Sideband Queue command, with lock parameter * @hw: pointer to the HW struct * @in: message info to be filled in descriptor + * @flag: flag to fill desc structure * @lock: true to lock the sq_lock (the usual case); false if the sq_lock has * already been locked at a higher level */ -int ice_sbq_rw_reg_lp(struct ice_hw *hw, - struct ice_sbq_msg_input *in, bool lock) +int ice_sbq_rw_reg_lp(struct ice_hw *hw, struct ice_sbq_msg_input *in, + u16 flag, bool lock) { struct ice_sbq_cmd_desc desc = {0}; struct ice_sbq_msg_req msg = {0}; @@ -1798,7 +1799,7 @@ int ice_sbq_rw_reg_lp(struct ice_hw *hw, */ msg_len -= sizeof(msg.data); - desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); + desc.flags = CPU_TO_LE16(flag); desc.opcode = CPU_TO_LE16(ice_sbq_opc_neigh_dev_req); desc.param0.cmd_len = CPU_TO_LE16(msg_len); if (lock) @@ -1816,10 +1817,11 @@ int ice_sbq_rw_reg_lp(struct ice_hw *hw, * ice_sbq_rw_reg - Fill Sideband Queue command * @hw: pointer to the HW struct * @in: message info to be filled in descriptor + * @flag: flag to fill desc structure */ -int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) +int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag) { - return ice_sbq_rw_reg_lp(hw, in, true); + return ice_sbq_rw_reg_lp(hw, in, flag, true); } /** diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index d06742aa77..2f1b212812 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -245,11 +245,11 @@ int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); void ice_replay_post(struct ice_hw *hw); struct ice_q_ctx * ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); -int ice_sbq_rw_reg_lp(struct ice_hw *hw, - struct ice_sbq_msg_input *in, bool lock); +int ice_sbq_rw_reg_lp(struct ice_hw *hw, struct ice_sbq_msg_input *in, + u16 flag, bool lock); void ice_sbq_lock(struct ice_hw *hw); void ice_sbq_unlock(struct ice_hw *hw); -int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in); +int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag); int ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format, struct ice_aqc_get_sensor_reading_resp *data, diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 77e30c2306..0d2968c528 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -122,7 +122,7 @@ ice_read_cgu_reg_e82x(struct ice_hw *hw, u16 addr, u32 *val) cgu_msg.msg_addr_low = addr; cgu_msg.msg_addr_high = 0x0; - err = ice_sbq_rw_reg_lp(hw, &cgu_msg, true); + err = ice_sbq_rw_reg_lp(hw, &cgu_msg, ICE_AQ_FLAG_RD, true); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", addr, err); @@ -155,7 +155,7 @@ ice_write_cgu_reg_e82x(struct ice_hw *hw, u16 addr, u32 val) cgu_msg.msg_addr_high = 0x0; cgu_msg.data = val; - err = ice_sbq_rw_reg_lp(hw, &cgu_msg, true); + err = ice_sbq_rw_reg_lp(hw, &cgu_msg, ICE_AQ_FLAG_RD, true); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", addr, err); @@ -948,7 +948,7 @@ ice_write_phy_eth56g_raw_lp(struct ice_hw *hw, u8 phy_index, u32 reg_addr, phy_msg.data = val; phy_msg.dest_dev = hw->phy_addr[phy_index]; - err = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &phy_msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", @@ -980,7 +980,7 @@ ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u8 phy_index, u32 reg_addr, phy_msg.data = 0; phy_msg.dest_dev = hw->phy_addr[phy_index]; - err = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &phy_msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", @@ -2530,7 +2530,7 @@ ice_read_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val, ice_fill_phy_msg_e822(&msg, port, offset); msg.opcode = ice_sbq_msg_rd; - err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", err); @@ -2663,7 +2663,7 @@ ice_write_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val, msg.opcode = ice_sbq_msg_wr; msg.data = val; - err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", err); @@ -2827,7 +2827,7 @@ ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val, msg.opcode = ice_sbq_msg_rd; - err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", err); @@ -2870,7 +2870,7 @@ ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val, msg.opcode = ice_sbq_msg_wr; msg.data = val; - err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", err); @@ -4700,7 +4700,7 @@ ice_read_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 *val, bool lock_sbq) msg.opcode = ice_sbq_msg_rd; msg.dest_dev = rmn_0; - err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", err); @@ -4738,7 +4738,7 @@ ice_write_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 val, bool lock_sbq) msg.dest_dev = rmn_0; msg.data = val; - err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); + err = ice_sbq_rw_reg_lp(hw, &msg, ICE_AQ_FLAG_RD, lock_sbq); if (err) { ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", err); -- 2.43.0