From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by dpdk.org (Postfix) with ESMTP id 361CCB57D for ; Fri, 20 Feb 2015 11:55:49 +0100 (CET) Received: by mail-wi0-f171.google.com with SMTP id hi2so2073421wib.4 for ; Fri, 20 Feb 2015 02:55:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=d8W0xACFFlvn4uA7RN4FKxFkftWhBqvaeyYXNbjh5ZY=; b=P9Bjh1y7B+Omg10KhFzZZHvznaUWQvspX4nmZk90Xkz7/GuEXrY4HUh0vZhxUhi/sT +OX0F6IbXlF3QR9NtP9AedfTsElWKTt0NQ6K3wQgs2A1gYRM5f1JE1VMXH6BqG++S5nH 0NSKh0KbQMMP8roX3G+qvjtiXt2BlyJAonVgKeCRqlkdu/YawnjZSmMYLtKfovQRhQDG vVFukLJeacNePkevmFsBV3XIooK6IMF2uOJ+ufbGTOuFNNWGPUfNAfdJOMrAoAA3k7Ob OdD741u+U2UHea5HHUW/Yukl5LIuLPjs6lA5kOdo4fEwy/usopdvhSa85HbvRE4Joho/ OlTA== X-Gm-Message-State: ALoCoQnqtyYC3wgLSzAfsWy78wRPqskd3UqdHwg956AeDbzYiuALmclxtskOjk22IN/pB3+Lq+do X-Received: by 10.180.91.47 with SMTP id cb15mr18419918wib.39.1424429745957; Fri, 20 Feb 2015 02:55:45 -0800 (PST) Received: from xps13.localnet (136-92-190-109.dsl.ovh.fr. [109.190.92.136]) by mx.google.com with ESMTPSA id lu13sm1849279wic.10.2015.02.20.02.55.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Feb 2015 02:55:45 -0800 (PST) From: Thomas Monjalon To: dev@dpdk.org Date: Fri, 20 Feb 2015 11:55:16 +0100 Message-ID: <7268152.GLh5O7JM1M@xps13> Organization: 6WIND User-Agent: KMail/4.14.4 (Linux/3.18.4-1-ARCH; KDE/4.14.4; x86_64; ; ) In-Reply-To: <1423637385-25077-1-git-send-email-xuelin.shi@freescale.com> References: <1423637385-25077-1-git-send-email-xuelin.shi@freescale.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe PCI and CPU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Feb 2015 10:55:49 -0000 Anyone to review this patch? 2015-02-11 14:49, xuelin.shi@freescale.com: > From: Xuelin Shi > > make sure: > CPU read from ixgbe with IXGBE_LE32_TO_CPUS > CPU write to ixgbe with IXGBE_CPU_TO_LE32 > > otherwise, there is endian issue for ixgbe on BIG_ENDIAN CPU. > > Signed-off-by: Xuelin Shi > --- > .../linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h | 24 ++++++++++++++++------ > 1 file changed, 18 insertions(+), 6 deletions(-) > > diff --git a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > index d161600..0612632 100644 > --- a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > +++ b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h > @@ -53,6 +53,16 @@ > > #undef ASSERT > > +static inline uint32_t ixgbe_read_addr(volatile void* addr) > +{ > + return IXGBE_LE32_TO_CPUS(*((volatile uint32_t *)addr)); > +} > + > +static inline uint32_t ixgbe_write_addr(u32 value, volatile void* addr) > +{ > + return writel(IXGBE_CPU_TO_LE32(value), addr); > +} > + > #ifdef DBG > #define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A) > #else > @@ -91,19 +101,20 @@ > default: \ > break; \ > } \ > - writel((value), ((a)->hw_addr + (reg))); \ > + ixgbe_write_addr((value), ((a)->hw_addr + (reg))); \ > } while (0) > #else > -#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg))) > +#define IXGBE_WRITE_REG(a, reg, value) \ > + ixgbe_write_addr((value), ((a)->hw_addr + (reg))) > #endif > > -#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg)) > +#define IXGBE_READ_REG(a, reg) ixgbe_read_addr((a)->hw_addr + (reg)) > > #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \ > - writel((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) > + ixgbe_write_addr((value), ((a)->hw_addr + (reg) + ((offset) << 2)))) > > #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \ > - readl((a)->hw_addr + (reg) + ((offset) << 2))) > + ixgbe_read_addr((a)->hw_addr + (reg) + ((offset) << 2))) > > #ifndef writeq > #define writeq(val, addr) do { writel((u32) (val), addr); \ > @@ -111,7 +122,8 @@ > } while (0); > #endif > > -#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg))) > +#define IXGBE_WRITE_REG64(a, reg, value) \ > + writeq((cpu_to_le64(value)), ((a)->hw_addr + (reg))) > > #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) > struct ixgbe_hw; >