From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3250AA04DC; Tue, 20 Oct 2020 13:56:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 12B73BBDA; Tue, 20 Oct 2020 13:56:55 +0200 (CEST) Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id E97CCBBDA for ; Tue, 20 Oct 2020 13:56:52 +0200 (CEST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.nyi.internal (Postfix) with ESMTP id 975605C013A; Tue, 20 Oct 2020 07:56:51 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Tue, 20 Oct 2020 07:56:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= mGIOXB3mQP67hAb3BtLD7dmqmgDFULmpjvOmMjQSGyg=; b=J96jYFsyIa/gXR/p Hnns/pyqKHK0BdYOSkkrJ7KDpHOohs7/xG9Km9QZoPTLppEW9gC68os9ClYfLXp8 GFEpEdxkpwD7gZtOlCGo5XksE/jLnWFxOiHQ+P2cKe8/5TJAUi8pJNaqMdomWR2Q /K1uUaWbcW33vL19MqoyghFUiFIWybNmeXYf3D2g7OJMKzfsgVGcXQEGm1Xr+9PE SXS8XihR+N6wy4q5g1UvtD/GH4HquhjdjH3cjFaqvNvd58k3L1V9NFo9WOSkntpX 1H0O8XPv/SxDuweaugPOQ5kKfqI3P5RPY+hWnini9FroOXk686N1e8KtmrmyWvi8 9q14RQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=mGIOXB3mQP67hAb3BtLD7dmqmgDFULmpjvOmMjQSG yg=; b=RQXz0ht9LDzK9vqzvDqbrLBig8JqHzkXOkfaWgveyaRJysNuLeQJTnkgk rC3zEoFTksL5IPH4ek21ti5LXLzoNzgUp7F6vZCzpVqaGgXG25iBmKHve+PkTj/X 6iybE+gSBX0vyzq16GmAiOKkPgyG/kEu6tDzIQcazOidjWqQXUkhrDaltsMHaWwI pDjKxZVilP6gTa+nSBf8zlwMVuOd3WeQtfYR9XfRWkdqQ3nidklAMkl7uZUzWalu Ytl9eGL9J6vXUy4T9nMoyfVUkzy2qNmO1zT+3OF4MoljxBxo4sFTXC56jtC9fs4v fUnGXK2Q+Y6GcLezOXY5l3evS/GqA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrjeefgdeghecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf frrghtthgvrhhnpeefgfevteffhfehveetueejjeduledtveeitedvvefgudeuhfelveej tdduuedvtdenucffohhmrghinheprghrmhdrtghomhdpihhnrhhirgdrfhhrnecukfhppe ejjedrudefgedrvddtfedrudekgeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgr mhepmhgrihhlfhhrohhmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 32F6D3280067; Tue, 20 Oct 2020 07:56:50 -0400 (EDT) From: Thomas Monjalon To: Honnappa Nagarahalli Cc: Phil Yang , dev@dpdk.org, nd , Diogo Behrens , david.marchand@redhat.com Date: Tue, 20 Oct 2020 13:56:49 +0200 Message-ID: <7423385.l6g0CaCsxP@thomas> In-Reply-To: <05e6a3569608493abbcc4dba618c5c2c@huawei.com> References: <20200826092002.19395-1-diogo.behrens@huawei.com> <1947647.zX4bR4m4Ni@thomas> <05e6a3569608493abbcc4dba618c5c2c@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] librte_eal: fix mcslock hang on weak memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Honnappa? 07/10/2020 11:55, Diogo Behrens: > Hi Thomas, > > we are still waiting for the comments from Honnappa. In our understanding, the missing barrier is a bug according to the model. We reproduced the scenario in herd7, which represents the authoritative memory model: https://developer.arm.com/architectures/cpu-architecture/a-profile/memory-model-tool > > Here is a litmus code that shows that the XCHG (when compiled to LDAXR and STLR) is not atomic wrt memory updates to other locations: > ----- > AArch64 XCHG-nonatomic > { > 0:X1=locked; 0:X3=next; > 1:X1=locked; 1:X3=next; 1:X5=tail; > } > P0 | P1; > LDR W0, [X3] | MOV W0, #1; > CBZ W0, end | STR W0, [X1]; (* init locked *) > MOV W2, #2 | MOV W2, #0; > STR W2, [X1] | xchg:; > end: | LDAXR W6, [X5]; > NOP | STLXR W4, W0, [X5]; > NOP | CBNZ W4, xchg; > NOP | STR W0, [X3]; (* set next *) > exists > (0:X2=2 /\ locked=1) > ----- > (web version of herd7: http://diy.inria.fr/www/?record=aarch64) > > P1 is trying to acquire the lock: > - initializes locked > - does the xchg on the tail of the mcslock > - sets the next > > P0 is releasing the lock: > - if next is not set, just terminates > - if next is set, stores 2 in locked > > The initialization of locked should never overwrite the store 2 to locked, but it does. > To avoid that reordering to happen, one should make the last store of P1 to have a "release" barrier, ie, STLR. > > This is equivalent to the reordering occurring in the mcslock of librte_eal. > > Best regards, > -Diogo > > -----Original Message----- > From: Thomas Monjalon [mailto:thomas@monjalon.net] > Sent: Tuesday, October 6, 2020 11:50 PM > To: Phil Yang ; Diogo Behrens ; Honnappa Nagarahalli > Cc: dev@dpdk.org; nd > Subject: Re: [dpdk-dev] [PATCH] librte_eal: fix mcslock hang on weak memory > > 31/08/2020 20:45, Honnappa Nagarahalli: > > > > Hi Diogo, > > > > Thanks for your explanation. > > > > As documented in https://developer.arm.com/documentation/ddi0487/fc B2.9.5 Load-Exclusive and Store-Exclusive instruction usage restrictions: > > " Between the Load-Exclusive and the Store-Exclusive, there are no > > explicit memory accesses, preloads, direct or indirect System register > > writes, address translation instructions, cache or TLB maintenance instructions, exception generating instructions, exception returns, or indirect branches." > > [Honnappa] This is a requirement on the software, not on the micro-architecture. > > We are having few discussions internally, will get back soon. > > > > So it is not allowed to insert (1) & (4) between (2, 3). The cmpxchg operation is atomic. > > > Please what is the conclusion?