From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B72A4A00BE; Mon, 16 May 2022 06:19:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5824040A79; Mon, 16 May 2022 06:19:41 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id B3614406A2 for ; Mon, 16 May 2022 06:19:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652674779; x=1684210779; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=bIuctYm/QoG0qILArAQKGyGBkmDM8aUJxGn3TS6pCbA=; b=Ekpg4vSuyMH5RmdJR9nbns9BR19FrHPKJtElZNtjla/Uqa4varQA8Ozj JEMo1PE/dtjobsaRJOSESG4g13c6/F376++DEl6+XzjwlFRZ6zzvuXdaM Eq2677XL93KlXiy0srsJv35/jSnKf+wBmSytX6F+Rb42s6LxhpoB4BhaI DfhybN0Vg7rjXB9yoyxCYVrTksoNdj9cbwT6oElOSYMSwAra0IIGGkNna yB/lz0Y+0T+ZrnUx7Dh6N0EmS9rycNS/CoTw3vMPUN9R2egqerrJAajrG DrNEQzuZ7nEwe5IFUJOLBG+YxE34MhawrahU9SYJFYR3m8RMMHAQdsLII Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10348"; a="258296723" X-IronPort-AV: E=Sophos;i="5.91,229,1647327600"; d="scan'208";a="258296723" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2022 21:19:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,229,1647327600"; d="scan'208";a="699362960" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by orsmga004.jf.intel.com with ESMTP; 15 May 2022 21:19:34 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Sun, 15 May 2022 21:19:34 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Sun, 15 May 2022 21:19:33 -0700 Received: from fmsmsx612.amr.corp.intel.com ([10.18.126.92]) by fmsmsx612.amr.corp.intel.com ([10.18.126.92]) with mapi id 15.01.2308.027; Sun, 15 May 2022 21:19:33 -0700 From: "Pei, Andy" To: "Xia, Chenbo" , "dev@dpdk.org" CC: "maxime.coquelin@redhat.com" , "Cao, Gang" , "Liu, Changpeng" Subject: RE: [PATCH v7 16/18] vdpa/ifc/base: access correct register for blk device Thread-Topic: [PATCH v7 16/18] vdpa/ifc/base: access correct register for blk device Thread-Index: AQHYWheLDMPSfLkibES9prCLD6rI560cNc+ggATOHZA= Date: Mon, 16 May 2022 04:19:33 +0000 Message-ID: <7593f43205f94251a5c10f17920b18c7@intel.com> References: <1643093258-47258-2-git-send-email-andy.pei@intel.com> <1651048206-282372-1-git-send-email-andy.pei@intel.com> <1651048206-282372-17-git-send-email-andy.pei@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.6.401.20 dlp-reaction: no-action x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org HI Chenbo, Thanks for your reply. I will send out a new version to fix this. > -----Original Message----- > From: Xia, Chenbo > Sent: Friday, May 13, 2022 10:58 AM > To: Pei, Andy ; dev@dpdk.org > Cc: maxime.coquelin@redhat.com; Cao, Gang ; Liu, > Changpeng > Subject: RE: [PATCH v7 16/18] vdpa/ifc/base: access correct register for = blk > device >=20 > > -----Original Message----- > > From: Pei, Andy > > Sent: Wednesday, April 27, 2022 4:30 PM > > To: dev@dpdk.org > > Cc: Xia, Chenbo ; maxime.coquelin@redhat.com; > > Cao, Gang ; Liu, Changpeng > > > > Subject: [PATCH v7 16/18] vdpa/ifc/base: access correct register for > > blk device > > > > 1.last_avail_idx is lower 16 bit of the register. > > 2.address of ring_state register is different between net and blk devic= e. >=20 > Not a good commit log. The commit log should illustrate more on what's th= e > commit is doing. >=20 > Thanks, > Chenbo >=20 > > > > Signed-off-by: Andy Pei > > --- > > drivers/vdpa/ifc/base/ifcvf.c | 36 > > +++++++++++++++++++++++++++++------- > > drivers/vdpa/ifc/base/ifcvf.h | 1 + > > 2 files changed, 30 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/vdpa/ifc/base/ifcvf.c > > b/drivers/vdpa/ifc/base/ifcvf.c index d10c1fd..4d5881a 100644 > > --- a/drivers/vdpa/ifc/base/ifcvf.c > > +++ b/drivers/vdpa/ifc/base/ifcvf.c > > @@ -218,10 +218,18 @@ > > &cfg->queue_used_hi); > > IFCVF_WRITE_REG16(hw->vring[i].size, &cfg->queue_size); > > > > - *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4) =3D > > - (u32)hw->vring[i].last_avail_idx | > > - ((u32)hw->vring[i].last_used_idx << 16); > > + if (hw->is_blk =3D=3D IFCVF_BLK) { > > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > > + i * IFCVF_LM_CFG_SIZE) =3D > > + (u32)hw->vring[i].last_avail_idx | > > + ((u32)hw->vring[i].last_used_idx << 16); > > + } else if (hw->is_blk =3D=3D IFCVF_NET) { > > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > > + (i / 2) * IFCVF_LM_CFG_SIZE + > > + (i % 2) * 4) =3D > > + (u32)hw->vring[i].last_avail_idx | > > + ((u32)hw->vring[i].last_used_idx << 16); > > + } > > > > IFCVF_WRITE_REG16(i + 1, &cfg->queue_msix_vector); > > if (IFCVF_READ_REG16(&cfg->queue_msix_vector) =3D=3D @@ - > 254,9 +262,23 > > @@ > > IFCVF_WRITE_REG16(i, &cfg->queue_select); > > IFCVF_WRITE_REG16(0, &cfg->queue_enable); > > IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg- > > >queue_msix_vector); > > - ring_state =3D *(u32 *)(hw->lm_cfg + > IFCVF_LM_RING_STATE_OFFSET > > + > > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4); > > - hw->vring[i].last_avail_idx =3D (u16)(ring_state >> 16); > > + > > + if (hw->is_blk) { > > + ring_state =3D *(u32 *)(hw->lm_cfg + > > + IFCVF_LM_RING_STATE_OFFSET + > > + i * IFCVF_LM_CFG_SIZE); > > + } else if (hw->is_blk =3D=3D IFCVF_NET) { > > + ring_state =3D *(u32 *)(hw->lm_cfg + > > + IFCVF_LM_RING_STATE_OFFSET + > > + (i / 2) * IFCVF_LM_CFG_SIZE + > > + (i % 2) * 4); > > + } > > + > > + if (hw->is_blk =3D=3D IFCVF_BLK) > > + hw->vring[i].last_avail_idx =3D > > + (u16)(ring_state & IFCVF_16_BIT_MASK); > > + else if (hw->is_blk =3D=3D IFCVF_NET) > > + hw->vring[i].last_avail_idx =3D (u16)(ring_state >> 16); > > hw->vring[i].last_used_idx =3D (u16)(ring_state >> 16); > > } > > } > > diff --git a/drivers/vdpa/ifc/base/ifcvf.h > > b/drivers/vdpa/ifc/base/ifcvf.h index 8591ef1..ff11b12 100644 > > --- a/drivers/vdpa/ifc/base/ifcvf.h > > +++ b/drivers/vdpa/ifc/base/ifcvf.h > > @@ -65,6 +65,7 @@ > > #define IFCVF_MEDIATED_VRING 0x200000000000 > > > > #define IFCVF_32_BIT_MASK 0xffffffff > > +#define IFCVF_16_BIT_MASK 0xffff > > > > #ifndef VHOST_USER_PROTOCOL_F_CONFIG > > #define VHOST_USER_PROTOCOL_F_CONFIG 9 > > -- > > 1.8.3.1 >=20