From: Sagi Grimberg <sagi@grimberg.me>
To: dev@dpdk.org, "Shahaf Shuler" <shahafs@mellanox.com>,
"Nélio Laranjeiro" <nelio.laranjeiro@6wind.com>,
"Yongseok Koh" <yskoh@mellanox.com>,
"Roy Shterman" <roys@lightbitslabs.com>,
"Alexander Solganik" <sashas@lightbitslabs.com>
Subject: [dpdk-dev] Question on mlx5 PMD txq memory registration
Date: Mon, 17 Jul 2017 16:29:34 +0300 [thread overview]
Message-ID: <75d08202-1882-7660-924c-b6dbb4455b88@grimberg.me> (raw)
Hi,
Looking at the code, it looks like mlx5 keeps a MR cache per TX queue
(each MR registers a rte_mempool).
Once a TX queue is created, mlx5 scans existing mempools and
pre-registers a MR for each mempool it meets (using rte_mempool_walk).
For each MR registration that exceeds the TX queue cache, it removes the
first entry from the cache and deregisters that MR (in txq_mp2mr_reg).
Now on TX burst, if the driver sees a mbuf from an unknown mempool, it
registers the mempool on the fly and again *deregister* the first MR in
the cache.
My question is, what guarantees that no inflight send operations posted
on the TX queue when we deregister and remove a MR from the cache?
AFAICT, it is the driver responsibility to guarantee to never deregister
a memory region that has inflight send operations posted, otherwise
the send operation *will* complete with a local protection error. Is
that taken care of?
Another question, why is the MR cache maintained per TX queue and not
per device? If the application starts N TX queues then a single mempool
will be registered N times instead of just once. Having lots of MR
instances will pollute the device ICMC pretty badly. Am I missing
something?
Thanks,
Sagi.
next reply other threads:[~2017-07-17 13:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-17 13:29 Sagi Grimberg [this message]
2017-07-17 21:02 ` Nélio Laranjeiro
2017-07-19 6:21 ` Sagi Grimberg
2017-07-20 13:55 ` Nélio Laranjeiro
2017-07-20 14:06 ` Sagi Grimberg
2017-07-20 15:20 ` Shahaf Shuler
2017-07-20 16:22 ` Sagi Grimberg
2017-07-23 8:17 ` Shahaf Shuler
2017-07-23 9:03 ` Sagi Grimberg
2017-07-24 13:44 ` Bruce Richardson
2017-07-27 10:48 ` Sagi Grimberg
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