From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 757D2A0509; Sat, 7 May 2022 02:52:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1C41640395; Sat, 7 May 2022 02:52:48 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 13DCD4014F for ; Sat, 7 May 2022 02:52:45 +0200 (CEST) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4Kw86C2NSqzhYwP; Sat, 7 May 2022 08:52:19 +0800 (CST) Received: from [127.0.0.1] (10.67.100.224) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Sat, 7 May 2022 08:52:42 +0800 Subject: Re: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k To: Rahul Bhansali , Ruifeng Wang , "dev@dpdk.org" , Jan Viktorin , Bruce Richardson CC: Jerin Jacob Kollanukkaran , nd References: <20220505142744.1423344-1-rbhansali@marvell.com> <20220505142744.1423344-2-rbhansali@marvell.com> <2e290e15-a438-2591-4b69-83ef9c2c8634@huawei.com> <556f5ec3-fcb2-b977-8739-6a3e8fffe4a1@huawei.com> From: fengchengwen Message-ID: <78cbcbf9-1495-cc2d-d11d-04ed4b21e206@huawei.com> Date: Sat, 7 May 2022 08:52:42 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.100.224] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 2022/5/6 21:17, Rahul Bhansali wrote: > > >> -----Original Message----- >> From: Ruifeng Wang >> Sent: Friday, May 6, 2022 12:53 PM >> To: fengchengwen ; Rahul Bhansali >> ; dev@dpdk.org; Jan Viktorin >> ; Bruce Richardson >> Cc: Jerin Jacob Kollanukkaran ; nd >> Subject: RE: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k >> >>> -----Original Message----- >>> From: fengchengwen >>> Sent: Friday, May 6, 2022 2:36 PM >>> To: Rahul Bhansali ; dev@dpdk.org; Ruifeng Wang >>> ; Jan Viktorin ; Bruce >>> Richardson >>> Cc: jerinj@marvell.com >>> Subject: Re: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k >>> >>> On 2022/5/6 12:54, Rahul Bhansali wrote: >>>> >>>> >>>>> -----Original Message----- >>>>> From: fengchengwen >>>>> Sent: Friday, May 6, 2022 8:00 AM >>>>> To: Rahul Bhansali ; dev@dpdk.org; Ruifeng >>>>> Wang ; Jan Viktorin >>> ; >>>>> Bruce Richardson >>>>> Cc: Jerin Jacob Kollanukkaran >>>>> Subject: [EXT] Re: [PATCH 2/2] config/arm: disable SVE for cn10k >>>>> >>>>> External Email >>>>> >>>>> ------------------------------------------------------------------- >>>>> -- >>>>> - On 2022/5/5 22:27, Rahul Bhansali wrote: >>>>>> This disable the SVE flag for cn10k. >>>>>> >>>>>> Performance impact:- >>>>>> With l3fwd example, lpm lookup performance increased by ~21% if >>> Neon >>>>>> is used instead of SVE. >>>>>> >>>>>> Signed-off-by: Rahul Bhansali >>>>>> --- >>>>>> config/arm/meson.build | 3 ++- >>>>>> 1 file changed, 2 insertions(+), 1 deletion(-) >>>>>> >>>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>>>>> dafb342cc6..39b7a1270c 100644 >>>>>> --- a/config/arm/meson.build >>>>>> +++ b/config/arm/meson.build >>>>>> @@ -281,7 +281,8 @@ soc_cn10k = { >>>>>> ], >>>>>> 'part_number': '0xd49', >>>>>> 'extra_march_features': ['crypto'], >>>>>> - 'numa': false >>>>>> + 'numa': false, >>>>>> + 'sve': false >>>>> >>>>> Suggest remove sve2 flag: >>>>> '0xd49': { >>>>> 'march': 'armv8.5-a', >>>>> 'march_features': ['sve2'], ---remove 'sve2' >>>>> 'flags': [ >>>>> ['RTE_MACHINE', '"neoverse-n2"'], >>>>> ['RTE_ARM_FEATURE_ATOMICS', true], >>>>> ['RTE_MAX_LCORE', 64], >>>>> ['RTE_MAX_NUMA_NODES', 1] >>>>> ] >>>>> } >>>>> >>>> If I remove here, then this will also change for " Arm Neoverse N2 >>>> soc_n2", >>> because part_number is same, Right ? >>>> Because of this reason, I thought to have separate flag instead of >>>> updating >>> march_features. >>> >>> This new add flag only impact hand-writen sve code, but >>> auto-vectorization is also enabled when sve is enabled at march_features. >> Agree. >> >>> Maybe NEON-based automated vector code performs better than SVE- >>> based. >>> >>> I think it's OK to add separate flag in soc_xxx struct, but suggest it >>> also impact auto-vectorization. >> I would suggest the flag to control only RTE_HAS_SVE_ACLE, i.e. hand written >> code using SVE C language intrinsics. >> For auto-vectorization, I think it is compilers duty to vectorize in the most >> performant way, use whatever resource hardware provided. >> > > I agree to the point of auto-vectorization to let it be if supported and control the RTE_HAS_SVE_ACLE for hand-written SVE C code. Agree with the point: the flag to control only RTE_HAS_SVE_ACLE Maybe sve_acle is more appropriate for the new flag. > >>> >>> So for one soc which test or optimize well on sve, it could turn the flag to true. >>> >>>> >>>>>> } >>>>>> >>>>>> soc_dpaa = { >>>>>> >>>> >