From: Xiaoyun wang <cloud.wangxiaoyun@huawei.com>
To: <dev@dpdk.org>
Cc: <ferruh.yigit@intel.com>, <bluca@debian.org>,
<luoxianjun@huawei.com>, <luoxingyu@huawei.com>,
<zhouguoyang@huawei.com>, <yin.yinshi@huawei.com>,
<david.yangxiaoliang@huawei.com>, <zhaohui8@huawei.com>,
<zhengjingzhou@huawei.com>, <guojian365@huawei.com>,
Xiaoyun wang <cloud.wangxiaoyun@huawei.com>, <stable@dpdk.org>
Subject: [dpdk-dev] [PATCH v1 2/4] net/hinic: optimize Rx performance for x86
Date: Sat, 25 Jul 2020 11:48:23 +0800 [thread overview]
Message-ID: <806d3d4f94ae0f8b6bcfd78ae3211259bc06978e.1595648149.git.cloud.wangxiaoyun@huawei.com> (raw)
In-Reply-To: <cover.1595648149.git.cloud.wangxiaoyun@huawei.com>
For x86 platform, the rq cqe without cache aligned, which can
improve performace for some gateway scenarios.
Fixes: 361a9ccf81d6 ("net/hinic: optimize Rx performance")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun wang <cloud.wangxiaoyun@huawei.com>
---
drivers/net/hinic/hinic_pmd_rx.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/hinic/hinic_pmd_rx.h b/drivers/net/hinic/hinic_pmd_rx.h
index 49fa565..8a45f2d 100644
--- a/drivers/net/hinic/hinic_pmd_rx.h
+++ b/drivers/net/hinic/hinic_pmd_rx.h
@@ -35,7 +35,11 @@ struct hinic_rq_cqe {
u32 rss_hash;
u32 rsvd[4];
+#if defined(RTE_ARCH_ARM64)
} __rte_cache_aligned;
+#else
+};
+#endif
struct hinic_rq_cqe_sect {
struct hinic_sge sge;
--
1.8.3.1
next prev parent reply other threads:[~2020-07-25 3:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-25 3:48 [dpdk-dev] [PATCH v1 0/4] some bugs fixes Xiaoyun wang
2020-07-25 3:48 ` [dpdk-dev] [PATCH v1 1/4] net/hinic: modify csum offload process Xiaoyun wang
2020-07-25 3:48 ` Xiaoyun wang [this message]
2020-07-25 3:48 ` [dpdk-dev] [PATCH v1 3/4] net/hinic/base: modify vhd type for SDI Xiaoyun wang
2020-07-25 3:48 ` [dpdk-dev] [PATCH v1 4/4] net/hinic/base: make timeout not affected by system time jump Xiaoyun wang
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