From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 832F5A034C; Tue, 18 Aug 2020 10:06:34 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5D6921C022; Tue, 18 Aug 2020 10:06:34 +0200 (CEST) Received: from mail.chinasoftinc.com (unknown [114.113.233.8]) by dpdk.org (Postfix) with ESMTP id C7220AAB7 for ; Tue, 18 Aug 2020 10:06:32 +0200 (CEST) Received: from [192.168.1.199] (139.159.243.11) by INCCAS001.ito.icss (10.168.0.60) with Microsoft SMTP Server id 14.3.487.0; Tue, 18 Aug 2020 16:06:32 +0800 To: Ruifeng Wang , "dev@dpdk.org" CC: "xavier.huwei@huawei.com" , nd , Honnappa Nagarahalli , "jerinjacobk@gmail.com" References: <20200817124703.58157-1-huwei013@chinasoftinc.com> <20200818024355.23364-1-huwei013@chinasoftinc.com> From: "Wei Hu (Xavier)" Message-ID: <80db8a4c-ba3c-7591-775b-94a6a4e467d3@chinasoftinc.com> Date: Tue, 18 Aug 2020 16:06:30 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Originating-IP: [139.159.243.11] Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH v3] eal/arm64: update CPU flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Ruifeng Wang On 2020/8/18 11:41, Ruifeng Wang wrote: > Hi, > >> -----Original Message----- >> From: Wei Hu (Xavier) >> Sent: Tuesday, August 18, 2020 10:44 AM >> To: dev@dpdk.org >> Cc: xavier.huwei@huawei.com; nd ; Honnappa Nagarahalli >> ; Ruifeng Wang >> ; jerinjacobk@gmail.com >> Subject: [PATCH v3] eal/arm64: update CPU flags >> >> From: "Wei Hu (Xavier)" >> >> SVE is the next-generation SIMD extension of the ARMv8-A AArch64 >> instruction set. >> The related marco definition can be found in linux kernel: >> arch/arm64/include/uapi/asm/hwcap.h >> >> This patch updates cpu SVE flags on ARM64 platform, such as SVE, etc. >> >> Signed-off-by: Chengwen Feng >> Signed-off-by: Wei Hu (Xavier) >> --- >> v2 -> v3: >> 1. Change commit log. >> 2. Add HWCAP2_FLAGM2 and HWCAP2_FRINT to >> rte_cpu_feature_table[]. >> 3. Add the flags for newly added items into enum rte_cpu_flag_t. >> v1 -> v2: >> Adds more sve-related definition to rte_cpu_feature_table, >> sunch as SVE2, etc. >> --- >> lib/librte_eal/arm/include/rte_cpuflags_64.h | 13 +++++++++++++ >> lib/librte_eal/arm/rte_cpuflags.c | 13 +++++++++++++ >> 2 files changed, 26 insertions(+) >> > How about updating test_cpuflags() too to cover these new flags? OK, I will update it in V4. Thanks Xavier > Thanks. > /Ruifeng >> diff --git a/lib/librte_eal/arm/include/rte_cpuflags_64.h >> b/lib/librte_eal/arm/include/rte_cpuflags_64.h >> index 95cc01474..aa7a56d49 100644 >> --- a/lib/librte_eal/arm/include/rte_cpuflags_64.h >> +++ b/lib/librte_eal/arm/include/rte_cpuflags_64.h >> @@ -22,6 +22,19 @@ enum rte_cpu_flag_t { >> RTE_CPUFLAG_SHA2, >> RTE_CPUFLAG_CRC32, >> RTE_CPUFLAG_ATOMICS, >> + RTE_CPUFLAG_SVE, >> + RTE_CPUFLAG_SVE2, >> + RTE_CPUFLAG_SVEAES, >> + RTE_CPUFLAG_SVEPMULL, >> + RTE_CPUFLAG_SVEBITPERM, >> + RTE_CPUFLAG_SVESHA3, >> + RTE_CPUFLAG_SVESM4, >> + RTE_CPUFLAG_FLAGM2, >> + RTE_CPUFLAG_FRINT, >> + RTE_CPUFLAG_SVEI8MM, >> + RTE_CPUFLAG_SVEF32MM, >> + RTE_CPUFLAG_SVEF64MM, >> + RTE_CPUFLAG_SVEBF16, >> RTE_CPUFLAG_AARCH64, >> /* The last item */ >> RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ >> diff --git a/lib/librte_eal/arm/rte_cpuflags.c >> b/lib/librte_eal/arm/rte_cpuflags.c >> index caf3dc83a..7b257b787 100644 >> --- a/lib/librte_eal/arm/rte_cpuflags.c >> +++ b/lib/librte_eal/arm/rte_cpuflags.c >> @@ -95,6 +95,19 @@ const struct feature_entry rte_cpu_feature_table[] = { >> FEAT_DEF(SHA2, REG_HWCAP, 6) >> FEAT_DEF(CRC32, REG_HWCAP, 7) >> FEAT_DEF(ATOMICS, REG_HWCAP, 8) >> + FEAT_DEF(SVE, REG_HWCAP, 22) >> + FEAT_DEF(SVE2, REG_HWCAP2, 1) >> + FEAT_DEF(SVEAES, REG_HWCAP2, 2) >> + FEAT_DEF(SVEPMULL, REG_HWCAP2, 3) >> + FEAT_DEF(SVEBITPERM, REG_HWCAP2, 4) >> + FEAT_DEF(SVESHA3, REG_HWCAP2, 5) >> + FEAT_DEF(SVESM4, REG_HWCAP2, 6) >> + FEAT_DEF(FLAGM2, REG_HWCAP2, 7) >> + FEAT_DEF(FRINT, REG_HWCAP2, 8) >> + FEAT_DEF(SVEI8MM, REG_HWCAP2, 9) >> + FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) >> + FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) >> + FEAT_DEF(SVEBF16, REG_HWCAP2, 12) >> FEAT_DEF(AARCH64, REG_PLATFORM, 1) >> }; >> #endif /* RTE_ARCH */ >> -- >> 2.27.0