From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-eopbgr10066.outbound.protection.outlook.com [40.107.1.66]) by dpdk.org (Postfix) with ESMTP id B5B514CA7 for ; Fri, 12 Apr 2019 03:59:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BTPrqzpLZ4CglaE6OSQwDr4f7VtB/g2P0vEdCwWIhXc=; b=YsuZ485T+Poy+Dv9/0VHZ49gOd58f9fA/fL+R2RITluPtkVR8pKFGyX/OOEZPAN8lpi1vWtQmeQeKta0JWR4DgVR7XhqT2fKciA9z0lWyDlpGyI2Rv3eQp170fdxbWAFvcolhd8/elDoeZ9OyfKJaIXQSDTsy//GNCd4mQ6tt48= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3945.eurprd05.prod.outlook.com (52.134.65.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.16; Fri, 12 Apr 2019 01:59:04 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Fri, 12 Apr 2019 01:59:04 +0000 From: Yongseok Koh To: Thomas Monjalon CC: Pavan Nikhilesh , Jerin Jacob , dev , "jerinjacobk@gmail.com" , "bruce.richardson@intel.com" Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y3n5YAgAAnlQA= Date: Fri, 12 Apr 2019 01:59:04 +0000 Message-ID: <815F48D0-E35D-4DD7-B795-582538D0BF4E@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> <7046361.HPUSkOkSIl@xps> In-Reply-To: <7046361.HPUSkOkSIl@xps> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1968970b-115a-4d1e-73e3-08d6beea7116 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:DB3PR0502MB3945; x-ms-traffictypediagnostic: DB3PR0502MB3945: x-ld-processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtAddr x-microsoft-antispam-prvs: x-forefront-prvs: 0005B05917 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(136003)(366004)(39860400002)(376002)(396003)(189003)(199004)(6246003)(86362001)(71190400001)(486006)(8936002)(97736004)(186003)(68736007)(14454004)(76176011)(229853002)(82746002)(83716004)(102836004)(53546011)(99286004)(6506007)(8676002)(53936002)(81156014)(81166006)(446003)(2616005)(71200400001)(6916009)(54906003)(11346002)(476003)(478600001)(316002)(2906002)(66066001)(93886005)(3846002)(6116002)(106356001)(105586002)(7736002)(305945005)(6486002)(6436002)(5660300002)(33656002)(26005)(4326008)(256004)(25786009)(36756003)(6512007); DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3945; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: mF65/y8674Obia+BZu/F2CYeUuV1zdcn6Buu5Vn1mK2l6JHO+d2ttIoHFcqp68NeYUtWLjJj2BJjo3eovWtqReGGudlQOLUIwB/k90ZlhKpTlJ7Djf4naKUtPBixU3amRPzntjqKAN29+afsYn+ny4Pk7NHA+089MqTSuCr97WiVy1PKk+L9QuE6+x6cu/c5GwG/Znf4b78DCWpnrl8VPkLkIjACmbx/z8MULiYBi6uUbVXSer5vCbYtqwVb7F92E5Yc7jcl8HMMgB9IoaAyLAZ1C8d7Hjv1P2Y23So7mcBB0epgwz2zFxmav6w8/vdzyDgmoTFCTZffeCnw/0KQPEPkekcdF9EE2ibtzeZebMnfove8GE9q6q5ikiokxFjZc0LkeSfLWsfGBLbtqshK6r9WC+cYWGCXPCBLnugceQw= Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1968970b-115a-4d1e-73e3-08d6beea7116 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 01:59:04.7094 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3945 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Apr 2019 01:59:08 -0000 > On Apr 11, 2019, at 4:37 PM, Thomas Monjalon wrote: >=20 > 10/04/2019 18:13, jerinjacobk@gmail.com: >> From: Pavan Nikhilesh >>=20 >> Currently, RTE_* flags are set based on the implementer ID but there mig= ht >> be some micro arch specific differences from the same vendor >> eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >=20 > I don't like how flags are set in config/arm/meson.build. > It is a real mess to find which flag applies to which machine. > Adding the flags_*_extra in the machine_args_* is adding more mess. >=20 > [...] >> flags_common_default =3D [ >> # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest= ) >> # to determine the best threshold in code. Refer to notes in source fil= e >> @@ -52,12 +33,10 @@ flags_generic =3D [ >> ['RTE_USE_C11_MEM_MODEL', true], >> ['RTE_CACHE_LINE_SIZE', 128]] >> flags_cavium =3D [ >> - ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> ['RTE_MAX_NUMA_NODES', 2], >> ['RTE_MAX_LCORE', 96], >> - ['RTE_MAX_VFIO_GROUPS', 128], >> - ['RTE_USE_C11_MEM_MODEL', false]] >> + ['RTE_MAX_VFIO_GROUPS', 128]] >> flags_dpaa =3D [ >> ['RTE_MACHINE', '"dpaa"'], >> ['RTE_USE_C11_MEM_MODEL', true], >> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >> ['RTE_MAX_NUMA_NODES', 1], >> ['RTE_MAX_LCORE', 16], >> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >> +flags_default_extra =3D [] >> +flags_thunderx_extra =3D [ >> + ['RTE_MACHINE', '"thunderx"'], >> + ['RTE_USE_C11_MEM_MODEL', false]] >> + >> +machine_args_generic =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['native', ['-march=3Dnative']], >> + ['0xd03', ['-mcpu=3Dcortex-a53']], >> + ['0xd04', ['-mcpu=3Dcortex-a35']], >> + ['0xd07', ['-mcpu=3Dcortex-a57']], >> + ['0xd08', ['-mcpu=3Dcortex-a72']], >> + ['0xd09', ['-mcpu=3Dcortex-a73']], >> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + >> +machine_args_cavium =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> + ['native', ['-march=3Dnative']], >> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > I think we should have a simpler model. > We need only to know the machine name and get all the related machine con= fig. > In native compilation, machine name is guessed from implementor id and pn It can be guessed unless machine name is specified as an option. We can add machine_name option? One observation. We do have machine option but it isn't used much for arm. And in config/arm/meson.build, march_opt isn't used either. > (from config/arm/armv8_machine.py). We can directly output the machine na= me > from this script and leave the naming logic in this script. > In the cross-compilation config files (config/arm/*), > we can just specify the machine name. > Then every machine config (machine_args and dpdk_conf) would be specified > in some arrays based on the machine name. > Of course, we can keep some common default values. >=20 > Thoughts? Sounds like we can cleanly reorganize it with the suggestion. Thanks, Yongseok= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 8711FA0096 for ; Fri, 12 Apr 2019 03:59:10 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7C50D4CAB; Fri, 12 Apr 2019 03:59:09 +0200 (CEST) Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-eopbgr10066.outbound.protection.outlook.com [40.107.1.66]) by dpdk.org (Postfix) with ESMTP id B5B514CA7 for ; Fri, 12 Apr 2019 03:59:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BTPrqzpLZ4CglaE6OSQwDr4f7VtB/g2P0vEdCwWIhXc=; b=YsuZ485T+Poy+Dv9/0VHZ49gOd58f9fA/fL+R2RITluPtkVR8pKFGyX/OOEZPAN8lpi1vWtQmeQeKta0JWR4DgVR7XhqT2fKciA9z0lWyDlpGyI2Rv3eQp170fdxbWAFvcolhd8/elDoeZ9OyfKJaIXQSDTsy//GNCd4mQ6tt48= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3945.eurprd05.prod.outlook.com (52.134.65.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.16; Fri, 12 Apr 2019 01:59:04 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Fri, 12 Apr 2019 01:59:04 +0000 From: Yongseok Koh To: Thomas Monjalon CC: Pavan Nikhilesh , Jerin Jacob , dev , "jerinjacobk@gmail.com" , "bruce.richardson@intel.com" Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y3n5YAgAAnlQA= Date: Fri, 12 Apr 2019 01:59:04 +0000 Message-ID: <815F48D0-E35D-4DD7-B795-582538D0BF4E@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> <7046361.HPUSkOkSIl@xps> In-Reply-To: <7046361.HPUSkOkSIl@xps> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3945; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: mF65/y8674Obia+BZu/F2CYeUuV1zdcn6Buu5Vn1mK2l6JHO+d2ttIoHFcqp68NeYUtWLjJj2BJjo3eovWtqReGGudlQOLUIwB/k90ZlhKpTlJ7Djf4naKUtPBixU3amRPzntjqKAN29+afsYn+ny4Pk7NHA+089MqTSuCr97WiVy1PKk+L9QuE6+x6cu/c5GwG/Znf4b78DCWpnrl8VPkLkIjACmbx/z8MULiYBi6uUbVXSer5vCbYtqwVb7F92E5Yc7jcl8HMMgB9IoaAyLAZ1C8d7Hjv1P2Y23So7mcBB0epgwz2zFxmav6w8/vdzyDgmoTFCTZffeCnw/0KQPEPkekcdF9EE2ibtzeZebMnfove8GE9q6q5ikiokxFjZc0LkeSfLWsfGBLbtqshK6r9WC+cYWGCXPCBLnugceQw= Content-Type: text/plain; charset="UTF-8" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1968970b-115a-4d1e-73e3-08d6beea7116 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 01:59:04.7094 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3945 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190412015904.5IQPCcVWhePtBAQcEtAKUfHNxZxr-MOlXPNlGIw40wY@z> > On Apr 11, 2019, at 4:37 PM, Thomas Monjalon wrote: >=20 > 10/04/2019 18:13, jerinjacobk@gmail.com: >> From: Pavan Nikhilesh >>=20 >> Currently, RTE_* flags are set based on the implementer ID but there mig= ht >> be some micro arch specific differences from the same vendor >> eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >=20 > I don't like how flags are set in config/arm/meson.build. > It is a real mess to find which flag applies to which machine. > Adding the flags_*_extra in the machine_args_* is adding more mess. >=20 > [...] >> flags_common_default =3D [ >> # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest= ) >> # to determine the best threshold in code. Refer to notes in source fil= e >> @@ -52,12 +33,10 @@ flags_generic =3D [ >> ['RTE_USE_C11_MEM_MODEL', true], >> ['RTE_CACHE_LINE_SIZE', 128]] >> flags_cavium =3D [ >> - ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> ['RTE_MAX_NUMA_NODES', 2], >> ['RTE_MAX_LCORE', 96], >> - ['RTE_MAX_VFIO_GROUPS', 128], >> - ['RTE_USE_C11_MEM_MODEL', false]] >> + ['RTE_MAX_VFIO_GROUPS', 128]] >> flags_dpaa =3D [ >> ['RTE_MACHINE', '"dpaa"'], >> ['RTE_USE_C11_MEM_MODEL', true], >> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >> ['RTE_MAX_NUMA_NODES', 1], >> ['RTE_MAX_LCORE', 16], >> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >> +flags_default_extra =3D [] >> +flags_thunderx_extra =3D [ >> + ['RTE_MACHINE', '"thunderx"'], >> + ['RTE_USE_C11_MEM_MODEL', false]] >> + >> +machine_args_generic =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['native', ['-march=3Dnative']], >> + ['0xd03', ['-mcpu=3Dcortex-a53']], >> + ['0xd04', ['-mcpu=3Dcortex-a35']], >> + ['0xd07', ['-mcpu=3Dcortex-a57']], >> + ['0xd08', ['-mcpu=3Dcortex-a72']], >> + ['0xd09', ['-mcpu=3Dcortex-a73']], >> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + >> +machine_args_cavium =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> + ['native', ['-march=3Dnative']], >> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > I think we should have a simpler model. > We need only to know the machine name and get all the related machine con= fig. > In native compilation, machine name is guessed from implementor id and pn It can be guessed unless machine name is specified as an option. We can add machine_name option? One observation. We do have machine option but it isn't used much for arm. And in config/arm/meson.build, march_opt isn't used either. > (from config/arm/armv8_machine.py). We can directly output the machine na= me > from this script and leave the naming logic in this script. > In the cross-compilation config files (config/arm/*), > we can just specify the machine name. > Then every machine config (machine_args and dpdk_conf) would be specified > in some arrays based on the machine name. > Of course, we can keep some common default values. >=20 > Thoughts? Sounds like we can cleanly reorganize it with the suggestion. Thanks, Yongseok=