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Mon, 15 Apr 2019 18:43:41 +0000 From: Yongseok Koh To: Jerin Jacob Kollanukkaran CC: "bruce.richardson@intel.com" , Pavan Nikhilesh Bhagavatula , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "gavin.hu@arm.com" , "Honnappa.Nagarahalli@arm.com" , dpdk-on-arm Thread-Topic: [EXT] [PATCH 5/6] build: add option for armv8 crypto extension Thread-Index: AQHU8cm5b8SJPn5CW0moCR+0z+ooT6Y9krUA Date: Mon, 15 Apr 2019 18:43:40 +0000 Message-ID: <8328F59C-14DF-412E-A8F7-6AA1F5061065@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-6-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9f1d4cb8-df93-41e0-4d40-08d6c1d247bf x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600140)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); 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charset="us-ascii" Content-ID: <2523BF962D3F3648A7C2BF30A1675B62@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f1d4cb8-df93-41e0-4d40-08d6c1d247bf X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 18:43:40.9035 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4042 Subject: Re: [dpdk-dev] [EXT] [PATCH 5/6] build: add option for armv8 crypto extension X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Apr 2019 18:43:43 -0000 > On Apr 13, 2019, at 12:22 AM, Jerin Jacob Kollanukkaran wrote: >=20 >> -----Original Message----- >> From: Yongseok Koh >> Sent: Saturday, April 13, 2019 4:55 AM >> To: bruce.richardson@intel.com; Jerin Jacob Kollanukkaran >> ; Pavan Nikhilesh Bhagavatula >> ; shahafs@mellanox.com >> Cc: dev@dpdk.org; thomas@monjalon.net; gavin.hu@arm.com; >> Honnappa.Nagarahalli@arm.com >> Subject: [EXT] [PATCH 5/6] build: add option for armv8 crypto extension >>=20 >> CONFIG_RTE_MACHINE=3D"armv8a" >> +CONFIG_RTE_ENABLE_ARMV8_CRYPTO=3Dy >=20 > This approach is not scalable. Even, it is not good for BlueField as you= =20 > you need to maintain two images. >=20 > Unlike other CPU flags, arm64's crypto cpu flag is really _optional_. > Access to crypto instructions is always at under runtime check. > See the following in rte_armv8_pmd.c >=20 >=20 > /* Check CPU for support for AES instruction set */ > if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) { > ARMV8_CRYPTO_LOG_ERR( > "AES instructions not supported by CPU"); > return -EFAULT; > } >=20 > /* Check CPU for support for SHA instruction set */ > if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA1) || > !rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA2)) { > ARMV8_CRYPTO_LOG_ERR( > "SHA1/SHA2 instructions not supported by CPU"); > return -EFAULT; > } >=20 > So In order to avoid one more config flags specific to armv8 in meson and= makefile build infra > And avoid the need for 6/6 patch. IMO, > # Introduce optional CPU flag scheme in eal. Treat armv8 crypto as option= al flag > # Skip the eal init check for optional flag. >=20 > Do you see any issues with that approach? I also thought about that approach and that was my number 1 priority. But, = I had one question came to my mind. Maybe, arm people can confirm it. Is it 100% guaranteed that compiler never makes use of any of crypto instructions even= if there's no specific asm/intrinsic code? The crypto extension has aes, pmul= l, sha1 and sha2. In case of rte_memcpy() for x86, for example, compiler may optimize code using avx512f instructions even though it is written specific= ally with avx2 intrinsics (__mm256_*) unless avx512f is disabled. If a complier expert in arm (or anyone else) confirm it is completely **optional**, then I'd love to take that approach for sure. Copied dpdk-on-arm ML. Thanks, Yongseok From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id D5AAFA00E6 for ; Mon, 15 Apr 2019 20:43:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EBD7A4C8D; Mon, 15 Apr 2019 20:43:43 +0200 (CEST) Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50064.outbound.protection.outlook.com [40.107.5.64]) by dpdk.org (Postfix) with ESMTP id C1F6C3256 for ; Mon, 15 Apr 2019 20:43:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ql9hspU1eR9JjXE87yfUC8zeS49ovfzWEEEDnMrP+Yo=; b=r2uQ21jsNIsQeLZU7+N+dcTlAKUMo5tA4Pyw/5PoQGN5hj86gqHUZg/+A5Lqiun+EPHzOkNT91BLY0AoDGuy852kIBvLvMXLMIC1XZWwPApSW70cd35/Y2zHWJ1AFTw3t2xsKS94XT/MDcgAavbsE7L8oyonAYsUX/2jdB4n/Qs= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB4042.eurprd05.prod.outlook.com (52.134.68.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.14; Mon, 15 Apr 2019 18:43:41 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.018; Mon, 15 Apr 2019 18:43:41 +0000 From: Yongseok Koh To: Jerin Jacob Kollanukkaran CC: "bruce.richardson@intel.com" , Pavan Nikhilesh Bhagavatula , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "gavin.hu@arm.com" , "Honnappa.Nagarahalli@arm.com" , dpdk-on-arm Thread-Topic: [EXT] [PATCH 5/6] build: add option for armv8 crypto extension Thread-Index: AQHU8cm5b8SJPn5CW0moCR+0z+ooT6Y9krUA Date: Mon, 15 Apr 2019 18:43:40 +0000 Message-ID: <8328F59C-14DF-412E-A8F7-6AA1F5061065@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-6-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB4042; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: u5jqZLmP/cyt7fH4nt78aC8L2n86OJtEqVuolyzcQZagBkuhWDTRr0WH3geOeKvBOnh7nXyF1VhcvfCGeyCL8jZrflFF32uhTdwILQDOP3F1ZbVRqa6uotGahelZXpE4JeW9SttiDnpKMM/v0FOjtYRWXrYrisa/R61vAX3SiAOEsom7hOz0EV1PVespqU4z2QiQxDO3yNJoKTOWIJaovr7mu+GK8/lGsXcvVbujxB0ac7R7BHdG3TLq3CeRy4/nEc4mAcR1AIxx/y6HHI1XR+6q2lmHp55lkN0PnylSx6AjqXXk0cATbhAs59KdKHNZIX/PC+eX8SyM7RJU+/admjhFC0A1rnTIydYh7xqouVUuUwyvdhr/9LmGvle1G3F9+WUKb/GI5H1mKZhHTJHQ3BB8XY9PWyxu3RYuKwBN9go= Content-Type: text/plain; charset="UTF-8" Content-ID: <2523BF962D3F3648A7C2BF30A1675B62@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f1d4cb8-df93-41e0-4d40-08d6c1d247bf X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 18:43:40.9035 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4042 Subject: Re: [dpdk-dev] [EXT] [PATCH 5/6] build: add option for armv8 crypto extension X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190415184340.qXD9DYdCg6KGp1JHrXczIWvD3VW_NYFq-iGtXI8ie6o@z> > On Apr 13, 2019, at 12:22 AM, Jerin Jacob Kollanukkaran wrote: >=20 >> -----Original Message----- >> From: Yongseok Koh >> Sent: Saturday, April 13, 2019 4:55 AM >> To: bruce.richardson@intel.com; Jerin Jacob Kollanukkaran >> ; Pavan Nikhilesh Bhagavatula >> ; shahafs@mellanox.com >> Cc: dev@dpdk.org; thomas@monjalon.net; gavin.hu@arm.com; >> Honnappa.Nagarahalli@arm.com >> Subject: [EXT] [PATCH 5/6] build: add option for armv8 crypto extension >>=20 >> CONFIG_RTE_MACHINE=3D"armv8a" >> +CONFIG_RTE_ENABLE_ARMV8_CRYPTO=3Dy >=20 > This approach is not scalable. Even, it is not good for BlueField as you= =20 > you need to maintain two images. >=20 > Unlike other CPU flags, arm64's crypto cpu flag is really _optional_. > Access to crypto instructions is always at under runtime check. > See the following in rte_armv8_pmd.c >=20 >=20 > /* Check CPU for support for AES instruction set */ > if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) { > ARMV8_CRYPTO_LOG_ERR( > "AES instructions not supported by CPU"); > return -EFAULT; > } >=20 > /* Check CPU for support for SHA instruction set */ > if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA1) || > !rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA2)) { > ARMV8_CRYPTO_LOG_ERR( > "SHA1/SHA2 instructions not supported by CPU"); > return -EFAULT; > } >=20 > So In order to avoid one more config flags specific to armv8 in meson and= makefile build infra > And avoid the need for 6/6 patch. IMO, > # Introduce optional CPU flag scheme in eal. Treat armv8 crypto as option= al flag > # Skip the eal init check for optional flag. >=20 > Do you see any issues with that approach? I also thought about that approach and that was my number 1 priority. But, = I had one question came to my mind. Maybe, arm people can confirm it. Is it 100% guaranteed that compiler never makes use of any of crypto instructions even= if there's no specific asm/intrinsic code? The crypto extension has aes, pmul= l, sha1 and sha2. In case of rte_memcpy() for x86, for example, compiler may optimize code using avx512f instructions even though it is written specific= ally with avx2 intrinsics (__mm256_*) unless avx512f is disabled. If a complier expert in arm (or anyone else) confirm it is completely **optional**, then I'd love to take that approach for sure. Copied dpdk-on-arm ML. Thanks, Yongseok