From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62278A04FD; Wed, 20 Jul 2022 12:16:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0B7B140697; Wed, 20 Jul 2022 12:16:46 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id 463474003C for ; Wed, 20 Jul 2022 12:16:43 +0200 (CEST) Received: from localhost.localdomain (unknown [10.20.42.60]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxz9EG1tdiXmYqAA--.38915S3; Wed, 20 Jul 2022 18:16:40 +0800 (CST) Subject: Re: [v3 01/24] eal/loongarch: add atomic operations for LoongArch To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com, jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru Cc: dev@dpdk.org, maobibo@loongson.cn References: <20220606131054.2097526-1-zhoumin@loongson.cn> <20220606131054.2097526-2-zhoumin@loongson.cn> From: zhoumin Message-ID: <84f55f02-12da-ea7d-ab0e-fd26086b997e@loongson.cn> Date: Wed, 20 Jul 2022 18:16:38 +0800 User-Agent: Mozilla/5.0 (X11; Linux mips64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20220606131054.2097526-2-zhoumin@loongson.cn> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID: AQAAf9Dxz9EG1tdiXmYqAA--.38915S3 X-Coremail-Antispam: 1UD129KBjvJXoWxtr1xWFW7GrWrZF1UXF4Utwb_yoW3Cw4xpF W3CFnFgrsaqFy7J3s7Xr4rGwn5A34I9a4UXrW5G34kZFsFkr47Jay8Jr10vFy8Ga97Ary5 CrsYkFWUGr47GrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9G14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvEwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka 0xkIwI1lc7I2V7IY0VAS07AlzVAYIcxG8wCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I 8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AK xVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcV AFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8I cIk0rVWrZr1j6s0DMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI 0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-CM-SenderInfo: 52kr3ztlq6z05rqj20fqof0/ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Ping for review or feedback for this new arch support. Thanks, Min On 2022年06月06日 21:10, Min Zhou wrote: > This patch adds architecture specific atomic operations for > LoongArch architecture. These implementations use standard atomics > of toolchain and heavily reference generic atomics codes. > > Signed-off-by: Min Zhou > --- > lib/eal/loongarch/include/rte_atomic.h | 253 +++++++++++++++++++++++++ > 1 file changed, 253 insertions(+) > create mode 100644 lib/eal/loongarch/include/rte_atomic.h > > diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h > new file mode 100644 > index 0000000000..8e007e7f76 > --- /dev/null > +++ b/lib/eal/loongarch/include/rte_atomic.h > @@ -0,0 +1,253 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Loongson Technology Corporation Limited > + */ > + > +#ifndef _RTE_ATOMIC_LOONGARCH_H_ > +#define _RTE_ATOMIC_LOONGARCH_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include > +#include "generic/rte_atomic.h" > + > +/** > + * LoongArch Synchronize > + */ > +static inline void synchronize(void) > +{ > + __asm__ __volatile__("dbar 0":::"memory"); > +} > + > +/** > + * General memory barrier. > + * > + * Guarantees that the LOAD and STORE operations generated before the > + * barrier occur before the LOAD and STORE operations generated after. > + * This function is architecture dependent. > + */ > +#define rte_mb() synchronize() > + > +/** > + * Write memory barrier. > + * > + * Guarantees that the STORE operations generated before the barrier > + * occur before the STORE operations generated after. > + * This function is architecture dependent. > + */ > +#define rte_wmb() synchronize() > + > +/** > + * Read memory barrier. > + * > + * Guarantees that the LOAD operations generated before the barrier > + * occur before the LOAD operations generated after. > + * This function is architecture dependent. > + */ > +#define rte_rmb() synchronize() > + > +#define rte_smp_mb() rte_mb() > + > +#define rte_smp_wmb() rte_mb() > + > +#define rte_smp_rmb() rte_mb() > + > +#define rte_io_mb() rte_mb() > + > +#define rte_io_wmb() rte_mb() > + > +#define rte_io_rmb() rte_mb() > + > +static __rte_always_inline void > +rte_atomic_thread_fence(int memorder) > +{ > + __atomic_thread_fence(memorder); > +} > + > +#ifndef RTE_FORCE_INTRINSICS > +/*------------------------- 16 bit atomic operations -------------------------*/ > +static inline int > +rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src) > +{ > + return __sync_bool_compare_and_swap(dst, exp, src); > +} > + > +static inline uint16_t > +rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val) > +{ > +#if defined(__clang__) > + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST); > +#else > + return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST); > +#endif > +} > + > +static inline void > +rte_atomic16_inc(rte_atomic16_t *v) > +{ > + rte_atomic16_add(v, 1); > +} > + > +static inline void > +rte_atomic16_dec(rte_atomic16_t *v) > +{ > + rte_atomic16_sub(v, 1); > +} > + > +static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v) > +{ > + return __sync_add_and_fetch(&v->cnt, 1) == 0; > +} > + > +static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v) > +{ > + return __sync_sub_and_fetch(&v->cnt, 1) == 0; > +} > + > +static inline int rte_atomic16_test_and_set(rte_atomic16_t *v) > +{ > + return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1); > +} > + > +/*------------------------- 32 bit atomic operations -------------------------*/ > +static inline int > +rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src) > +{ > + return __sync_bool_compare_and_swap(dst, exp, src); > +} > + > +static inline uint32_t > +rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val) > +{ > +#if defined(__clang__) > + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST); > +#else > + return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST); > +#endif > +} > + > +static inline void > +rte_atomic32_inc(rte_atomic32_t *v) > +{ > + rte_atomic32_add(v, 1); > +} > + > +static inline void > +rte_atomic32_dec(rte_atomic32_t *v) > +{ > + rte_atomic32_sub(v, 1); > +} > + > +static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v) > +{ > + return __sync_add_and_fetch(&v->cnt, 1) == 0; > +} > + > +static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v) > +{ > + return __sync_sub_and_fetch(&v->cnt, 1) == 0; > +} > + > +static inline int rte_atomic32_test_and_set(rte_atomic32_t *v) > +{ > + return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1); > +} > + > +/*------------------------- 64 bit atomic operations -------------------------*/ > +static inline int > +rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src) > +{ > + return __sync_bool_compare_and_swap(dst, exp, src); > +} > + > +static inline uint64_t > +rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val) > +{ > +#if defined(__clang__) > + return __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST); > +#else > + return __atomic_exchange_8(dst, val, __ATOMIC_SEQ_CST); > +#endif > +} > + > +static inline void > +rte_atomic64_init(rte_atomic64_t *v) > +{ > + v->cnt = 0; > +} > + > +static inline int64_t > +rte_atomic64_read(rte_atomic64_t *v) > +{ > + return v->cnt; > +} > + > +static inline void > +rte_atomic64_set(rte_atomic64_t *v, int64_t new_value) > +{ > + v->cnt = new_value; > +} > + > +static inline void > +rte_atomic64_add(rte_atomic64_t *v, int64_t inc) > +{ > + __sync_fetch_and_add(&v->cnt, inc); > +} > + > +static inline void > +rte_atomic64_sub(rte_atomic64_t *v, int64_t dec) > +{ > + __sync_fetch_and_sub(&v->cnt, dec); > +} > + > +static inline void > +rte_atomic64_inc(rte_atomic64_t *v) > +{ > + rte_atomic64_add(v, 1); > +} > + > +static inline void > +rte_atomic64_dec(rte_atomic64_t *v) > +{ > + rte_atomic64_sub(v, 1); > +} > + > +static inline int64_t > +rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc) > +{ > + return __sync_add_and_fetch(&v->cnt, inc); > +} > + > +static inline int64_t > +rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec) > +{ > + return __sync_sub_and_fetch(&v->cnt, dec); > +} > + > +static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v) > +{ > + return rte_atomic64_add_return(v, 1) == 0; > +} > + > +static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v) > +{ > + return rte_atomic64_sub_return(v, 1) == 0; > +} > + > +static inline int rte_atomic64_test_and_set(rte_atomic64_t *v) > +{ > + return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1); > +} > + > +static inline void rte_atomic64_clear(rte_atomic64_t *v) > +{ > + rte_atomic64_set(v, 0); > +} > +#endif > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_ATOMIC_LOONGARCH_H_ */ -- 本邮件及其附件含有龙芯中科的商业秘密信息，仅限于发送给上面地址中列出的个人或群组。禁止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制或散发）本邮件及其附件中的信息。如果您错收本邮件，请您立即电话或邮件通知发件人并删除本邮件。 This email and its attachments contain confidential information from Loongson Technology , which is intended only for the person or entity whose address is listed above. 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