From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D53D4454EF; Tue, 25 Jun 2024 13:25:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ED11D42F06; Tue, 25 Jun 2024 13:18:33 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id BB71642D8C for ; Tue, 25 Jun 2024 13:17:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314231; x=1750850231; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MzZ88g6WBfC18JsnAb7mFYj45NsCUihfP+DX/CecjBo=; b=YmtPusdvnrNu+m2979wduQ77UALBlhQ+MxZLqmS+2iRnS2jj3v5prsrk gMVghuzJ+4QDAr5x6Nm905SEYXhIm7Sb3914qehpxpLGcImkx5O3SLge4 V/zRwy59EIY4kSUt1ZZzS7ArPJg3dC8QhIFweK/SvB+MYakHL6Ry2BQTJ RS1ieDPg/AUWTZyeqWfot65BzuYtHWNNIxZ1d9Ekx1OmOlqlaQynjbSbP jMnWpeGOye9i5jbKwRD2moUWUbGHF9JnR/3WtR7v5UVvnrMtpfQVEDqzW eTYHse728qMpZEnAflC6JlRU5PTOXoye/camEZFFyZLVW6zFmU5XPoWP+ Q==; X-CSE-ConnectionGUID: cRCgpM4JQFqFO4wmO1IP/Q== X-CSE-MsgGUID: ICTexjILTnKMY9zdeyzKJg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080402" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080402" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:17:09 -0700 X-CSE-ConnectionGUID: uU4lE5aJR6mdn4KV3hJQkQ== X-CSE-MsgGUID: nPl7f1eARF2LIzMJE0AP8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719502" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:17:09 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Karol Kolacinski , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 081/129] net/ice/base: add PHY OFFSET_READY register clearing Date: Tue, 25 Jun 2024 12:13:26 +0100 Message-ID: <8df484248b7b5659d1aa171e3fbecb72e742bff8.1719313663.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Karol Kolacinski Add a possibility to mark all transmitted/received timestamps as invalid by clearing PHY OFFSET_READY registers. Signed-off-by: Karol Kolacinski Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 84 +++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 1 + 2 files changed, 85 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 9d77ae4c25..ba0880ea4c 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1981,6 +1981,38 @@ int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); } +/** + * ice_ptp_clear_phy_offset_ready_eth56g - Clear PHY OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +static int ice_ptp_clear_phy_offset_ready_eth56g(struct ice_hw *hw) +{ + u8 port; + + for (port = 0; port < hw->max_phy_port; port++) { + int err; + + err = ice_write_phy_reg_eth56g(hw, port, + PHY_REG_TX_OFFSET_READY, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return err; + } + + err = ice_write_phy_reg_eth56g(hw, port, + PHY_REG_RX_OFFSET_READY, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return err; + } + } + + return 0; +} + /** * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time * @hw: pointer to the HW struct @@ -4055,6 +4087,36 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) return 0; } +/** + * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +static int ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw) +{ + u8 port; + + for (port = 0; port < hw->phy_ports; port++) { + int err; + + err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return err; + } + + err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return err; + } + } + + return 0; +} + /** * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode * @hw: pointer to the HW struct @@ -5797,6 +5859,28 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true); } +/** + * ice_ptp_clear_phy_offset_ready - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw) +{ + switch (hw->phy_cfg) { + case ICE_PHY_ETH56G: + return ice_ptp_clear_phy_offset_ready_eth56g(hw); + case ICE_PHY_E830: + case ICE_PHY_E810: + return 0; + case ICE_PHY_E822: + return ice_ptp_clear_phy_offset_ready_e822(hw); + default: + return ICE_ERR_NOT_SUPPORTED; + } +} + /** * ice_read_phy_tstamp - Read a PHY timestamp from the timestamp block * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 0914bf4cf7..266c87baee 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -137,6 +137,7 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); int ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); +int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw); int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); int -- 2.43.0