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From: "Eads, Gage" <gage.eads@intel.com>
To: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, "dev@dpdk.org"
<dev@dpdk.org>
CC: "olivier.matz@6wind.com" <olivier.matz@6wind.com>,
"arybchenko@solarflare.com" <arybchenko@solarflare.com>, "Richardson, Bruce"
<bruce.richardson@intel.com>, "Ananyev, Konstantin"
<konstantin.ananyev@intel.com>, "Gavin Hu (Arm Technology China)"
<Gavin.Hu@arm.com>, nd <nd@arm.com>, "thomas@monjalon.net"
<thomas@monjalon.net>, nd <nd@arm.com>
Thread-Topic: [PATCH v3 1/8] stack: introduce rte stack library
Thread-Index: AQHU1CtVrsaMA7YCkEOnYy6dB4cOVqYgkw6AgAJQ+XCABNcfIIAACF7Q
Date: Mon, 1 Apr 2019 19:34:32 +0000
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References: <20190305164256.2367-1-gage.eads@intel.com>
<20190306144559.391-1-gage.eads@intel.com>
<20190306144559.391-2-gage.eads@intel.com>
<VE1PR08MB5149B4FD26B816BA51F7B58998590@VE1PR08MB5149.eurprd08.prod.outlook.com>
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Subject: Re: [dpdk-dev] [PATCH v3 1/8] stack: introduce rte stack library
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> -----Original Message-----
> From: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com]
> Sent: Monday, April 1, 2019 12:41 PM
> To: Eads, Gage <gage.eads@intel.com>; dev@dpdk.org
> Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, Bruce
> <bruce.richardson@intel.com>; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; nd <nd@arm.com>; thomas@monjalon.net; nd
> <nd@arm.com>
> Subject: RE: [PATCH v3 1/8] stack: introduce rte stack library
>=20
> >
> > > > +static ssize_t
> > > > +rte_stack_get_memsize(unsigned int count) {
> > > > + ssize_t sz =3D sizeof(struct rte_stack);
> > > > +
> > > > + /* Add padding to avoid false sharing conflicts */
> > > > + sz +=3D RTE_CACHE_LINE_ROUNDUP(count * sizeof(void *)) +
> > > > + 2 * RTE_CACHE_LINE_SIZE;
> > > I did not understand how the false sharing is caused and how this
> > > padding is solving the issue. Verbose comments would help.
> >
> > The additional padding (beyond the CACHE_LINE_ROUNDUP) is to prevent
> > false sharing caused by adjacent/next-line hardware prefetchers. I'll
> > address this.
> >
> Is it not a generic problem? Or is it specific to this library?
This is not limited to this library, but it only affects systems with (enab=
led) next-line prefetchers, for example Intel products with an L2 adjacent =
cache line prefetcher[1]. For those systems, additional padding can potenti=
ally improve performance. As I understand it, this was the reason behind th=
e 128B alignment added to rte_ring a couple years ago[2].
[1] https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-c=
ontrol-on-some-intel-processors
[2] http://mails.dpdk.org/archives/dev/2017-February/058613.html
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Mon, 1 Apr 2019 12:34:32 -0700
From: "Eads, Gage" <gage.eads@intel.com>
To: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, "dev@dpdk.org"
<dev@dpdk.org>
CC: "olivier.matz@6wind.com" <olivier.matz@6wind.com>,
"arybchenko@solarflare.com" <arybchenko@solarflare.com>, "Richardson, Bruce"
<bruce.richardson@intel.com>, "Ananyev, Konstantin"
<konstantin.ananyev@intel.com>, "Gavin Hu (Arm Technology China)"
<Gavin.Hu@arm.com>, nd <nd@arm.com>, "thomas@monjalon.net"
<thomas@monjalon.net>, nd <nd@arm.com>
Thread-Topic: [PATCH v3 1/8] stack: introduce rte stack library
Thread-Index: AQHU1CtVrsaMA7YCkEOnYy6dB4cOVqYgkw6AgAJQ+XCABNcfIIAACF7Q
Date: Mon, 1 Apr 2019 19:34:32 +0000
Message-ID:
<9184057F7FC11744A2107296B6B8EB1E5420E63B@FMSMSX108.amr.corp.intel.com>
References: <20190305164256.2367-1-gage.eads@intel.com>
<20190306144559.391-1-gage.eads@intel.com>
<20190306144559.391-2-gage.eads@intel.com>
<VE1PR08MB5149B4FD26B816BA51F7B58998590@VE1PR08MB5149.eurprd08.prod.outlook.com>
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Subject: Re: [dpdk-dev] [PATCH v3 1/8] stack: introduce rte stack library
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> -----Original Message-----
> From: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com]
> Sent: Monday, April 1, 2019 12:41 PM
> To: Eads, Gage <gage.eads@intel.com>; dev@dpdk.org
> Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, Bruce
> <bruce.richardson@intel.com>; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; nd <nd@arm.com>; thomas@monjalon.net; nd
> <nd@arm.com>
> Subject: RE: [PATCH v3 1/8] stack: introduce rte stack library
>=20
> >
> > > > +static ssize_t
> > > > +rte_stack_get_memsize(unsigned int count) {
> > > > + ssize_t sz =3D sizeof(struct rte_stack);
> > > > +
> > > > + /* Add padding to avoid false sharing conflicts */
> > > > + sz +=3D RTE_CACHE_LINE_ROUNDUP(count * sizeof(void *)) +
> > > > + 2 * RTE_CACHE_LINE_SIZE;
> > > I did not understand how the false sharing is caused and how this
> > > padding is solving the issue. Verbose comments would help.
> >
> > The additional padding (beyond the CACHE_LINE_ROUNDUP) is to prevent
> > false sharing caused by adjacent/next-line hardware prefetchers. I'll
> > address this.
> >
> Is it not a generic problem? Or is it specific to this library?
This is not limited to this library, but it only affects systems with (enab=
led) next-line prefetchers, for example Intel products with an L2 adjacent =
cache line prefetcher[1]. For those systems, additional padding can potenti=
ally improve performance. As I understand it, this was the reason behind th=
e 128B alignment added to rte_ring a couple years ago[2].
[1] https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-c=
ontrol-on-some-intel-processors
[2] http://mails.dpdk.org/archives/dev/2017-February/058613.html