From: Thomas Monjalon <thomas.monjalon@6wind.com>
To: "Chen, Jing D" <jing.d.chen@intel.com>
Cc: dev@dpdk.org, "He, Shaopeng" <shaopeng.he@intel.com>
Subject: Re: [dpdk-dev] [PATCH] fm10k: fix improper RETA table config
Date: Fri, 10 Jul 2015 13:42:08 -0700 (PDT) [thread overview]
Message-ID: <9269117.yoS7W69ync@xps13> (raw)
In-Reply-To: <533710CFB86FA344BFBF2D6802E60286046B6702@SHSMSX101.ccr.corp.intel.com>
2015-07-10 08:20, Qiu, Michael:
> On 7/10/2015 4:19 PM, Chen, Jing D wrote:
> > From: "Chen Jing D(Mark)" <jing.d.chen@intel.com>
> >
> > fm10k has 128 RETA entries in 32 registers, but it only initialized
> > first 32 when doing multiple rx queue configurations. This fix will
> > initialize all 128 entries instead.
> >
> > Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
>
> Acked-by: Michael Qiu <michael.qiu@intel.com>
Applied, thanks
prev parent reply other threads:[~2015-07-10 20:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-10 8:19 Chen Jing D(Mark)
2015-07-10 8:20 ` Qiu, Michael
2015-07-10 20:42 ` Thomas Monjalon [this message]
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