From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 691582BA8 for ; Thu, 16 Aug 2018 14:28:38 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2018 05:28:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,247,1531810800"; d="scan'208";a="225113408" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.56]) ([10.237.221.56]) by orsmga004.jf.intel.com with ESMTP; 16 Aug 2018 05:28:36 -0700 To: Jerin Jacob Cc: Kiran Kumar , dev@dpdk.org, Konstantin Ananyev , Bruce Richardson , Santosh Shukla References: <1533810233-7706-1-git-send-email-kkokkilagadda@caviumnetworks.com> <5debc6df-9bed-597a-03e2-510372b849e0@intel.com> <20180816065256.GA11266@jerin> From: Ferruh Yigit Openpgp: preference=signencrypt Autocrypt: addr=ferruh.yigit@intel.com; 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WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180816065256.GA11266@jerin> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] kni: fix kni rx fifo producer synchronization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Aug 2018 12:28:40 -0000 On 8/16/2018 7:52 AM, Jerin Jacob wrote: > -----Original Message----- >> Date: Thu, 9 Aug 2018 12:30:57 +0100 >> From: Ferruh Yigit >> To: Kiran Kumar >> CC: dev@dpdk.org, Jerin Jacob , Konstantin >> Ananyev , Bruce Richardson >> , Santosh Shukla >> >> Subject: Re: [dpdk-dev] [PATCH] kni: fix kni rx fifo producer >> synchronization >> User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 >> Thunderbird/52.9.1 >> >> >> On 8/9/2018 11:23 AM, Kiran Kumar wrote: >>> With existing code in kni_fifo_put, rx_q values are not being updated >>> before updating fifo_write. While reading rx_q in kni_net_rx_normal, >>> This is causing the sync issue on other core. So adding a write >>> barrier to make sure the values being synced before updating fifo_write. >>> >>> Fixes: 3fc5ca2f6352 ("kni: initial import") >>> >>> Signed-off-by: Kiran Kumar >>> --- >>> lib/librte_kni/rte_kni_fifo.h | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/lib/librte_kni/rte_kni_fifo.h b/lib/librte_kni/rte_kni_fifo.h >>> index ac26a8c..4d6b33e 100644 >>> --- a/lib/librte_kni/rte_kni_fifo.h >>> +++ b/lib/librte_kni/rte_kni_fifo.h >>> @@ -39,6 +39,7 @@ kni_fifo_put(struct rte_kni_fifo *fifo, void **data, unsigned num) >>> fifo->buffer[fifo_write] = data[i]; >>> fifo_write = new_write; >>> } >>> + rte_smp_wmb(); >>> fifo->write = fifo_write; >>> return i; >> >> For Intel this is just a compiler barrier so no issue but not sure if a memory >> barrier is required here, >> >> Related code block is: >> >> |- for (i = 0; i < num; i++) { >> || new_write = (new_write + 1) & (fifo->len - 1); >> || >> || if (new_write == fifo_read) >> || break; >> || fifo->buffer[fifo_write] = data[i]; >> || fifo_write = new_write; >> || } >> | fifo->write = fifo_write; >> >> "fifo_write" is updated in the loop, so there is a dependency to it for >> "fifo->write". Can memory writes be reordered when there is a dependency? > > From CPU0 compiler instruction generation perspective, It will take care of the > dependency. In weakly ordered machine, it does NOT grandees CPU1 sees > fifo->write as final write. > > So, IMO, This patch make sense. We are able to reproduce the problem on > arm64 machine with certain traffic. OK, thanks for clarification. > >> >> Cc'ed a few more people for comment.