From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EA2FE4588C; Wed, 28 Aug 2024 23:04:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 91339402BE; Wed, 28 Aug 2024 23:04:58 +0200 (CEST) Received: from dkmailrelay1.smartsharesystems.com (smartserver.smartsharesystems.com [77.243.40.215]) by mails.dpdk.org (Postfix) with ESMTP id C2EB640295 for ; Wed, 28 Aug 2024 23:04:56 +0200 (CEST) Received: from smartserver.smartsharesystems.com (smartserver.smartsharesys.local [192.168.4.10]) by dkmailrelay1.smartsharesystems.com (Postfix) with ESMTP id 625C623210; Wed, 28 Aug 2024 23:04:55 +0200 (CEST) Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Subject: memif insufficient padding Date: Wed, 28 Aug 2024 23:04:51 +0200 X-MimeOLE: Produced By Microsoft Exchange V6.5 Message-ID: <98CBD80474FA8B44BF855DF32C47DC35E9F674@smartserver.smartshare.dk> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: memif insufficient padding Thread-Index: Adr5jezFbjvJkxTeSSeXmyaJyDJ9pQ== From: =?iso-8859-1?Q?Morten_Br=F8rup?= To: "Jakub Grajciar" Cc: X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Jakub, While browsing virtual interfaces in DPDK, I noticed a possible = performance issue in the memif driver: If "head" and "tail" are accessed by different lcores, they are not = sufficiently far away from each other (and other hot fields) to prevent = false sharing-like effects on systems with a next-N-lines hardware = prefetcher, which will prefetch "tail" when fetching "head", and = prefetch "head" when fetching "flags". I suggest updating the structure somewhat like this: -#define MEMIF_CACHELINE_ALIGN_MARK(mark) \ - alignas(RTE_CACHE_LINE_SIZE) RTE_MARKER mark; - -typedef struct { - MEMIF_CACHELINE_ALIGN_MARK(cacheline0); +typedef struct __rte_cache_aligned { uint32_t cookie; /**< MEMIF_COOKIE */ uint16_t flags; /**< flags */ #define MEMIF_RING_FLAG_MASK_INT 1 /**< disable interrupt mode */ + RTE_CACHE_GUARD; /* isolate head from flags */ RTE_ATOMIC(uint16_t) head; /**< pointer to ring buffer head */ - MEMIF_CACHELINE_ALIGN_MARK(cacheline1); + RTE_CACHE_GUARD; /* isolate tail from head */ RTE_ATOMIC(uint16_t) tail; /**< pointer to ring buffer tail */ - MEMIF_CACHELINE_ALIGN_MARK(cacheline2); + RTE_CACHE_GUARD; /* isolate descriptors from tail */ - memif_desc_t desc[0]; /**< buffer descriptors */ + memif_desc_t desc[]; /**< buffer descriptors */ } memif_ring_t; Med venlig hilsen / Kind regards, -Morten Br=F8rup