From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EB46A046B for ; Thu, 27 Jun 2019 19:06:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 396C02BF4; Thu, 27 Jun 2019 19:06:36 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id E3BE82B82 for ; Thu, 27 Jun 2019 19:06:34 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jun 2019 10:06:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,424,1557212400"; d="scan'208";a="162701702" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga008.fm.intel.com with ESMTP; 27 Jun 2019 10:06:33 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 27 Jun 2019 10:06:33 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 27 Jun 2019 10:06:33 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.83]) by shsmsx102.ccr.corp.intel.com ([169.254.2.33]) with mapi id 14.03.0439.000; Fri, 28 Jun 2019 01:06:30 +0800 From: "Wu, Jingjing" To: "Li, Xiaoyun" , "Wiles, Keith" , "Liang, Cunming" , "Maslekar, Omkar" CC: "dev@dpdk.org" Thread-Topic: [PATCH v8 2/6] raw/ntb: add intel ntb support Thread-Index: AQHVK+6obxFkwfcWpEqLLArglW9Ad6avuWXQ Date: Thu, 27 Jun 2019 17:06:30 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F81146A3BA@SHSMSX103.ccr.corp.intel.com> References: <20190620102147.41557-1-xiaoyun.li@intel.com> <20190626071224.4819-1-xiaoyun.li@intel.com> <20190626071224.4819-3-xiaoyun.li@intel.com> In-Reply-To: <20190626071224.4819-3-xiaoyun.li@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWJiNTdhNGUtYzM2NC00NjNmLWIzYmEtYTYwNDczNGZlYzRmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoicks5NlwveFR1QkxEbE5ueGRabDBjdWZLN1dkSG9HdW5tRmY2a0R5M1NLeVNMclwvbWVFWjlkWk4yMW5TbTJRaDlHIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v8 2/6] raw/ntb: add intel ntb support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Few minor comments. > +static int > +intel_ntb_dev_init(struct rte_rawdev *dev) > +{ > + struct ntb_hw *hw =3D dev->dev_private; > + uint8_t reg_val, bar; > + int ret, i; > + > + if (hw =3D=3D NULL) { > + NTB_LOG(ERR, "Invalid device."); > + return -EINVAL; > + } > + > + ret =3D rte_pci_read_config(hw->pci_dev, ®_val, > + sizeof(reg_val), XEON_PPD_OFFSET); > + if (ret < 0) { > + NTB_LOG(ERR, "Cannot get NTB PPD (PCIe port definition)."); > + return -EIO; > + } > + > + /* Check connection topo type. Only support B2B. */ > + switch (reg_val & XEON_PPD_CONN_MASK) { > + case XEON_PPD_CONN_B2B: > + NTB_LOG(INFO, "Topo B2B (back to back) is using."); > + break; > + case XEON_PPD_CONN_TRANSPARENT: > + case XEON_PPD_CONN_RP: > + NTB_LOG(ERR, "Not supported conn topo. Please use B2B."); > + return -EINVAL; Do We need "default:" ? > + } > + > + /* Check device type. */ > + if (reg_val & XEON_PPD_DEV_DSD) { > + NTB_LOG(INFO, "DSD, Downstream Device."); > + hw->topo =3D NTB_TOPO_B2B_DSD; > + } else { > + NTB_LOG(INFO, "USD, Upstream device."); > + hw->topo =3D NTB_TOPO_B2B_USD; > + } > + > + /* Check if bar4 is split. Do not support split bar. */ > + if (reg_val & XEON_PPD_SPLIT_BAR_MASK) { > + NTB_LOG(ERR, "Do not support split bar."); > + return -EINVAL; > + } > + > + hw->hw_addr =3D (char *)hw->pci_dev->mem_resource[0].addr; > + > + hw->mw_cnt =3D XEON_MW_COUNT; > + hw->db_cnt =3D XEON_DB_COUNT; > + hw->spad_cnt =3D XEON_SPAD_COUNT; > + > + hw->mw_size =3D rte_zmalloc("uint64_t", > + hw->mw_cnt * sizeof(uint64_t), 0); > + for (i =3D 0; i < hw->mw_cnt; i++) { > + bar =3D intel_ntb_bar[i]; > + hw->mw_size[i] =3D hw->pci_dev->mem_resource[bar].len; > + } > + > + /* Reserve the last 2 spad registers for users. */ > + for (i =3D 0; i < NTB_SPAD_USER_MAX_NUM; i++) > + hw->spad_user_list[i] =3D hw->spad_cnt; > + hw->spad_user_list[0] =3D hw->spad_cnt - 2; > + hw->spad_user_list[1] =3D hw->spad_cnt - 1; How about: hw->spad_user_list[0] =3D hw->spad_cnt - 2; hw->spad_user_list[1] =3D hw->spad_cnt - 1; for (i =3D 2; i < NTB_SPAD_USER_MAX_NUM; i++) hw->spad_user_list[i] =3D hw->spad_cnt;