From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 40273A04FB; Thu, 26 Dec 2019 02:47:02 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3942A1BF30; Thu, 26 Dec 2019 02:47:01 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 03959F94; Thu, 26 Dec 2019 02:46:58 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Dec 2019 17:46:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,357,1571727600"; d="scan'208";a="214468956" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga007.fm.intel.com with ESMTP; 25 Dec 2019 17:46:57 -0800 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 25 Dec 2019 17:46:57 -0800 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 25 Dec 2019 17:46:55 -0800 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Wed, 25 Dec 2019 17:46:55 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.29]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.236]) with mapi id 14.03.0439.000; Thu, 26 Dec 2019 09:46:54 +0800 From: "Wu, Jingjing" To: "Li, Xiaoyun" CC: "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [PATCH] raw/ntb: fix write memory barrier issue Thread-Index: AQHVqraf11WW3tlWt0a3AaiD4UrV+KfLxt6w Date: Thu, 26 Dec 2019 01:46:54 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8115C8E0D@SHSMSX103.ccr.corp.intel.com> References: <20191204151916.12607-1-xiaoyun.li@intel.com> In-Reply-To: <20191204151916.12607-1-xiaoyun.li@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] raw/ntb: fix write memory barrier issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Li, Xiaoyun > Sent: Wednesday, December 4, 2019 11:19 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Li, Xiaoyun ; stable@dpdk.org > Subject: [PATCH] raw/ntb: fix write memory barrier issue >=20 > All buffers and ring info should be written before tail register update. > This patch relocates the write memory barrier before updating tail regist= er > to avoid potential issues. >=20 > Fixes: 11b5c7daf019 ("raw/ntb: add enqueue and dequeue functions") > Cc: stable@dpdk.org >=20 > Signed-off-by: Xiaoyun Li Acked-by: Jingjing Wu