From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id D83635A13 for ; Thu, 31 Dec 2015 01:38:46 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 30 Dec 2015 16:38:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,503,1444719600"; d="scan'208,217";a="872106006" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 30 Dec 2015 16:38:47 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 30 Dec 2015 16:38:45 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.183]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.220]) with mapi id 14.03.0248.002; Thu, 31 Dec 2015 08:38:44 +0800 From: "Wu, Jingjing" To: Yaacov Hazan Thread-Topic: Flow Director - big endian handling Thread-Index: AdFC2dsmcrsM00CWQmO0TyI0lqFRFAAiG1sQ Date: Thu, 31 Dec 2015 00:38:43 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8D6BEFC@SHSMSX104.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] Flow Director - big endian handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Dec 2015 00:38:47 -0000 Hi, Yaacov Thank you for pointing that. Actually, Intel's NIC expects big endian when set flow_director_filter, and= little endian when set flow_director_mask. But in rte_eth level, we need t= o make them consistent. I think what you say make sense, to leave the hand= ling bytes order to PMD or just keep consistency. I will work on that. Thanks a lot! Jingjing From: Yaacov Hazan [mailto:yaacovh@mellanox.com] Sent: Wednesday, December 30, 2015 5:57 PM To: Wu, Jingjing Cc: dev@dpdk.org Subject: Flow Director - big endian handling Hi JingJing, I looked at your patch for flow director - app/testpmd: update flow directo= r commands - a56335925919d26c81dec8accf31c39d2f790c5a. It seems there is some mismatch in the handling of big endian between the f= ilter and mask. In the cmd_flow_director_filter_parsed function, which add the filter value= s, you called to rte_cpu_to_be_16 for the vlan_tci and ports values. But in cmd_flow_director_mask_parsed function, which set the mask, you didn= 't called to rte_cpu_to_be_16 for those values (valn_tci & ports). Does Intel's NICs (or Intel's PMDs) expected form application side to handl= e the big endian in different way for the filter values and the mask values= ? If yes, it is very confusing from the application/user point of view. I think that it is more make sense to leave the decision and handling of th= e big endian to the PMD layer, or at least to keep consistency for the expe= cted handling in the application layer. Thanks, Yaacov.