From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 408AA11A2 for ; Wed, 20 Apr 2016 12:16:16 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 20 Apr 2016 03:16:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,509,1455004800"; d="scan'208";a="958895735" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga002.jf.intel.com with ESMTP; 20 Apr 2016 03:16:01 -0700 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 20 Apr 2016 03:16:01 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 20 Apr 2016 03:16:00 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.229]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.155]) with mapi id 14.03.0248.002; Wed, 20 Apr 2016 18:15:59 +0800 From: "Wu, Jingjing" To: "Tao, Zhe" , "dev@dpdk.org" Thread-Topic: [dpdk-dev][PATCH 3/3 v7] i40e: Add global reset support for i40e Thread-Index: AQHRhnJEdsWXTITxQkm1+35xUEFTaJ+Szg3A Date: Wed, 20 Apr 2016 10:15:58 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8E22332@SHSMSX103.ccr.corp.intel.com> References: <1458816499-705-1-git-send-email-zhe.tao@intel.com> <1458895321-21896-1-git-send-email-zhe.tao@intel.com> <1458895321-21896-4-git-send-email-zhe.tao@intel.com> In-Reply-To: <1458895321-21896-4-git-send-email-zhe.tao@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 3/3 v7] i40e: Add global reset support for i40e X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Apr 2016 10:16:16 -0000 Hi, zhe Beside hein's global reset concern. I have another comment: Do you copy the following codes from i40e kernel driver? Have You done the Protext IP scan for it? Just let you know that linux kernel is GPL liscense, we can Not just copy code from it without any modification. Thanks Jingjing > + > +/** > + * i40e_do_reset - Start a PF or Core Reset sequence > + * @pf: board private structure > + * @reset_flags: which reset is requested > + * > + * The essential difference in resets is that the PF Reset > + * doesn't clear the packet buffers, doesn't reset the PE > + * firmware, and doesn't bother the other PFs on the chip. > + **/ > +static void i40e_do_reset(struct i40e_hw *hw, u32 reset_flags) { > + u32 val; > + > + /* do the biggest reset indicated */ > + if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { > + /* Request a Global Reset > + * > + * This will start the chip's countdown to the actual full > + * chip reset event, and a warning interrupt to be sent > + * to all PFs, including the requestor. Our handler > + * for the warning interrupt will deal with the shutdown > + * and recovery of the switch setup. > + */ > + PMD_INIT_LOG(NOTICE, "GlobalR requested\n"); > + val =3D rd32(hw, I40E_GLGEN_RTRIG); > + val |=3D I40E_GLGEN_RTRIG_GLOBR_MASK; > + wr32(hw, I40E_GLGEN_RTRIG, val); > + } > + /* other reset operations are not supported now */ } > diff --git a/drivers/net/i40e/i40e_ethdev.h > b/drivers/net/i40e/i40e_ethdev.h index 09fb6e2..f2a2fcc 100644 > --- a/drivers/net/i40e/i40e_ethdev.h > +++ b/drivers/net/i40e/i40e_ethdev.h > @@ -108,6 +108,36 @@ enum i40e_flxpld_layer_idx { > I40E_FLXPLD_L4_IDX =3D 2, > I40E_MAX_FLXPLD_LAYER =3D 3, > }; > + > +/* driver state flags */ > +enum i40e_state_t { > + __I40E_TESTING, > + __I40E_CONFIG_BUSY, > + __I40E_CONFIG_DONE, > + __I40E_DOWN, > + __I40E_NEEDS_RESTART, > + __I40E_SERVICE_SCHED, > + __I40E_ADMINQ_EVENT_PENDING, > + __I40E_MDD_EVENT_PENDING, > + __I40E_VFLR_EVENT_PENDING, > + __I40E_RESET_RECOVERY_PENDING, > + __I40E_RESET_INTR_RECEIVED, > + __I40E_REINIT_REQUESTED, > + __I40E_PF_RESET_REQUESTED, > + __I40E_CORE_RESET_REQUESTED, > + __I40E_GLOBAL_RESET_REQUESTED, > + __I40E_EMP_RESET_REQUESTED, > + __I40E_EMP_RESET_INTR_RECEIVED, > + __I40E_FILTER_OVERFLOW_PROMISC, > + __I40E_SUSPENDED, > + __I40E_BAD_EEPROM, > + __I40E_DEBUG_MODE, > + __I40E_DOWN_REQUESTED, > + __I40E_FD_FLUSH_REQUESTED, > + __I40E_RESET_FAILED, > + __I40E_PORT_TX_SUSPENDED, > + __I40E_VF_DISABLE, > +}; > #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fie= lds > */ > #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask > words */ #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of > flexpayload words */ > -- > 2.1.4