From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E0EE5A04DB; Thu, 15 Oct 2020 11:28:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BD8741DD02; Thu, 15 Oct 2020 11:28:47 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 8EB4E1DCFF for ; Thu, 15 Oct 2020 11:28:45 +0200 (CEST) IronPort-SDR: FJl19kw8QoERimG/4XaJG80+uyLwirdCmr5KjW6XR48iVXMFoqPGkSTAoK1NPzwbBJp/ardK0v OWLzUmJjWuDg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="166422166" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="166422166" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 02:28:43 -0700 IronPort-SDR: X/G5JKL18gkhzeWAXCfsCG0tXaV5l06OCvXcxgr4uHK0D2hxlpMoOgvfb3vPGp/McIelIsp1GN fSkZbG9Xlbbg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="300245289" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by fmsmga007.fm.intel.com with ESMTP; 15 Oct 2020 02:28:43 -0700 Received: from shsmsx602.ccr.corp.intel.com (10.109.6.142) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 15 Oct 2020 02:28:42 -0700 Received: from shsmsx605.ccr.corp.intel.com (10.109.6.215) by SHSMSX602.ccr.corp.intel.com (10.109.6.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 15 Oct 2020 17:28:40 +0800 Received: from shsmsx605.ccr.corp.intel.com ([10.109.6.215]) by SHSMSX605.ccr.corp.intel.com ([10.109.6.215]) with mapi id 15.01.1713.004; Thu, 15 Oct 2020 17:28:40 +0800 From: "Cao, Yahui" To: "Yan, Zhirun" , "Zhang, Qi Z" , "dev@dpdk.org" CC: "Wang, Xiao W" , "Su, Simei" , "Guo, Junfeng" Thread-Topic: [PATCH v1 2/2] net/ice: support inner/outer L2/L3 field for FDIR Thread-Index: AQHWlWHSZQq8NLrzVESFlgQQKMBj1qmYfviA Date: Thu, 15 Oct 2020 09:28:40 +0000 Message-ID: <9dbce9fbf43d47868c2534530108bac3@intel.com> References: <20200928063146.668003-1-zhirun.yan@intel.com> <20200928063146.668003-3-zhirun.yan@intel.com> In-Reply-To: <20200928063146.668003-3-zhirun.yan@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1 2/2] net/ice: support inner/outer L2/L3 field for FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Yan, Zhirun > Sent: Monday, September 28, 2020 2:32 PM > To: Zhang, Qi Z ; dev@dpdk.org > Cc: Cao, Yahui ; Wang, Xiao W > ; Su, Simei ; Guo, Junfeng > ; Yan, Zhirun > Subject: [PATCH v1 2/2] net/ice: support inner/outer L2/L3 field for FDIR >=20 > Distinguish inner/outer fields for parse pattern. So FDIR for tunnel > can be more flexible. Enable VXLAN inner/outer L3/L4 different fields > for FDIR. >=20 > Signed-off-by: Zhirun Yan > --- > drivers/net/ice/ice_fdir_filter.c | 59 +++++++++++++++++++++++++++++-- > 1 file changed, 56 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir= _filter.c > index 175abcdd5..961528d17 100644 > --- a/drivers/net/ice/ice_fdir_filter.c > +++ b/drivers/net/ice/ice_fdir_filter.c > @@ -56,6 +56,11 @@ > ICE_INSET_SCTP_SRC_PORT | ICE_INSET_SCTP_DST_PORT) >=20 > #define ICE_FDIR_INSET_VXLAN_IPV4 (\ > + ICE_FDIR_INSET_ETH | \ > + ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ > + ICE_INSET_IPV4_TOS | \ > + ICE_INSET_UDP_DST_PORT | \ > + ICE_INSET_TUN_DMAC | ICE_INSET_TUN_SMAC | \ > ICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST) >=20 > #define ICE_FDIR_INSET_VXLAN_IPV4_TCP (\ > @@ -907,6 +912,7 @@ ice_fdir_input_set_parse(uint64_t inset, enum > ice_flow_field *field) > }; > static const struct ice_inset_map ice_inset_map[] =3D { > {ICE_INSET_DMAC, ICE_FLOW_FIELD_IDX_ETH_DA}, > + {ICE_INSET_SMAC, ICE_FLOW_FIELD_IDX_ETH_SA}, > {ICE_INSET_ETHERTYPE, ICE_FLOW_FIELD_IDX_ETH_TYPE}, > {ICE_INSET_IPV4_SRC, ICE_FLOW_FIELD_IDX_IPV4_SA}, > {ICE_INSET_IPV4_DST, ICE_FLOW_FIELD_IDX_IPV4_DA}, > @@ -1655,6 +1661,14 @@ ice_fdir_parse_pattern(__rte_unused struct ice_ada= pter *ad, > uint32_t vtc_flow_cpu; > uint16_t ether_type; > enum rte_flow_item_type next_type; > + bool is_outer_part =3D true; > + > + for (item =3D pattern; item->type !=3D RTE_FLOW_ITEM_TYPE_END; item++) > { > + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_VXLAN) { > + tunnel_type =3D ICE_FDIR_TUNNEL_TYPE_VXLAN; > + break; > + } > + } >=20 > for (item =3D pattern; item->type !=3D RTE_FLOW_ITEM_TYPE_END; item++) > { > if (item->last) { > @@ -1672,7 +1686,25 @@ ice_fdir_parse_pattern(__rte_unused struct ice_ada= pter *ad, > eth_mask =3D item->mask; > next_type =3D (item + 1)->type; >=20 > - if (eth_spec && eth_mask) { > + if (!(eth_spec && eth_mask)) > + break; > + > + /* handle outer L2 fields */ > + if (is_outer_part && tunnel_type =3D=3D ICE_FDIR_TUNNEL_TYPE_VXLAN) { > + if (!rte_is_zero_ether_addr(ð_mask->dst)) > { > + filter->outer_input_set |=3D ICE_INSET_DMAC; > + rte_memcpy(&filter->input.ext_data_outer.dst_mac, > + ð_spec->dst, > + RTE_ETHER_ADDR_LEN); > + } > + > + if (!rte_is_zero_ether_addr(ð_mask->src)) { > + filter->outer_input_set |=3DICE_INSET_SMAC; > + rte_memcpy(&filter->input.ext_data_outer.src_mac, > + ð_spec->src, > + RTE_ETHER_ADDR_LEN); > + } > + } else { > if (!rte_is_zero_ether_addr(ð_mask->dst)) > { > input_set |=3D ICE_INSET_DMAC; > rte_memcpy(&filter->input.ext_data.dst_mac, > @@ -1714,7 +1746,27 @@ ice_fdir_parse_pattern(__rte_unused struct ice_ada= pter *ad, > ipv4_spec =3D item->spec; > ipv4_mask =3D item->mask; >=20 > - if (ipv4_spec && ipv4_mask) { > + if (!(ipv4_spec && ipv4_mask)) > + break; > + [Cao, Yahui]=20 It seems below code has quite some duplication with code within the else co= ndition Can you use a pointer *input_set and *ip to point to the different input_s= et bits and input_set value, So that existing code can be reused. > + /* handle outer L3 fields */ > + if (is_outer_part && tunnel_type =3D=3D ICE_FDIR_TUNNEL_TYPE_VXLAN) { > + if (ipv4_mask->hdr.dst_addr =3D=3D UINT32_MAX) { > + filter->outer_input_set |=3D ICE_INSET_IPV4_DST; > + filter->input.ip_outer.v4.dst_ip =3D > + ipv4_spec->hdr.dst_addr; > + } > + if (ipv4_mask->hdr.src_addr =3D=3D UINT32_MAX) { > + filter->outer_input_set |=3D ICE_INSET_IPV4_SRC; > + filter->input.ip_outer.v4.src_ip =3D > + ipv4_spec->hdr.src_addr; > + } > + if (ipv4_mask->hdr.type_of_service =3D=3D UINT8_MAX) { > + input_set |=3D ICE_INSET_IPV4_TOS; [Cao, Yahui]=20 Why use input_set instead of filter->outer_input_set in the VXLAN outer sec= tion ? > + filter->input.ip_outer.v4.tos =3D > + ipv4_spec->hdr.type_of_service; > + } > + } else { > /* Check IPv4 mask and update input set */ > if (ipv4_mask->hdr.version_ihl || > ipv4_mask->hdr.total_length || > @@ -1944,6 +1996,8 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adap= ter *ad, > break; > case RTE_FLOW_ITEM_TYPE_VXLAN: > l3 =3D RTE_FLOW_ITEM_TYPE_END; > + is_outer_part =3D false; > + > vxlan_spec =3D item->spec; > vxlan_mask =3D item->mask; >=20 > @@ -1955,7 +2009,6 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adap= ter *ad, > return -rte_errno; > } >=20 > - tunnel_type =3D ICE_FDIR_TUNNEL_TYPE_VXLAN; > break; > case RTE_FLOW_ITEM_TYPE_GTPU: > l3 =3D RTE_FLOW_ITEM_TYPE_END; > -- > 2.25.1