From: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
To: dev@dpdk.org
Cc: kumaras@chelsio.com, surendra@chelsio.com, nirranjan@chelsio.com,
indranil@chelsio.com
Subject: [dpdk-dev] [PATCH v2 1/7] cxgbe: rework rte_eth_dev allocation
Date: Wed, 28 Feb 2018 23:34:46 +0530 [thread overview]
Message-ID: <9e7f7a59dd443bcc1d2ec987d0b0c5b4973d75a6.1519832644.git.rahul.lakkireddy@chelsio.com> (raw)
In-Reply-To: <cover.1519832644.git.rahul.lakkireddy@chelsio.com>
In-Reply-To: <cover.1519832644.git.rahul.lakkireddy@chelsio.com>
Rework rte_eth_dev allocation for other ports under same PF.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
---
v2:
- Split rte_eth_dev allocation rework from patch 1.
drivers/net/cxgbe/base/adapter.h | 28 ++++++++++-----------
drivers/net/cxgbe/cxgbe_main.c | 53 +++++++++++++++++++++++-----------------
2 files changed, 44 insertions(+), 37 deletions(-)
diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h
index f2057af14..d96499987 100644
--- a/drivers/net/cxgbe/base/adapter.h
+++ b/drivers/net/cxgbe/base/adapter.h
@@ -308,7 +308,7 @@ struct adapter {
struct rte_pci_device *pdev; /* associated rte pci device */
struct rte_eth_dev *eth_dev; /* first port's rte eth device */
struct adapter_params params; /* adapter parameters */
- struct port_info port[MAX_NPORTS]; /* ports belonging to this adapter */
+ struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */
struct sge sge; /* associated SGE */
/* support for single-threading access to adapter mailbox registers */
@@ -327,6 +327,18 @@ struct adapter {
int use_unpacked_mode; /* unpacked rx mode state */
};
+/**
+ * adap2pinfo - return the port_info of a port
+ * @adap: the adapter
+ * @idx: the port index
+ *
+ * Return the port_info structure for the port of the given index.
+ */
+static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx)
+{
+ return adap->port[idx];
+}
+
#define CXGBE_PCI_REG(reg) rte_read32(reg)
static inline uint64_t cxgbe_read_addr64(volatile void *addr)
@@ -602,7 +614,7 @@ static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap)
static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
u8 hw_addr[])
{
- struct port_info *pi = &adapter->port[port_idx];
+ struct port_info *pi = adap2pinfo(adapter, port_idx);
ether_addr_copy((struct ether_addr *)hw_addr,
&pi->eth_dev->data->mac_addrs[0]);
@@ -687,18 +699,6 @@ static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
t4_os_unlock(lock);
}
-/**
- * adap2pinfo - return the port_info of a port
- * @adap: the adapter
- * @idx: the port index
- *
- * Return the port_info structure for the port of the given index.
- */
-static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
-{
- return &adap->port[idx];
-}
-
void *t4_alloc_mem(size_t size);
void t4_free_mem(void *addr);
#define t4_os_alloc(_size) t4_alloc_mem((_size))
diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c
index 28db6c061..553834749 100644
--- a/drivers/net/cxgbe/cxgbe_main.c
+++ b/drivers/net/cxgbe/cxgbe_main.c
@@ -382,7 +382,7 @@ static void print_port_info(struct adapter *adap)
struct rte_pci_addr *loc = &adap->pdev->addr;
for_each_port(adap, i) {
- const struct port_info *pi = &adap->port[i];
+ const struct port_info *pi = adap2pinfo(adap, i);
char *bufp = buf;
if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
@@ -860,7 +860,7 @@ void t4_os_portmod_changed(const struct adapter *adap, int port_id)
NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
};
- const struct port_info *pi = &adap->port[port_id];
+ const struct port_info *pi = adap2pinfo(adap, port_id);
if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
@@ -1190,6 +1190,11 @@ void cxgbe_close(struct adapter *adapter)
t4_free_vi(adapter, adapter->mbox,
adapter->pf, 0, pi->viid);
rte_free(pi->eth_dev->data->mac_addrs);
+ /* Skip first port since it'll be freed by DPDK stack */
+ if (!i) {
+ rte_free(pi->eth_dev->data->dev_private);
+ rte_eth_dev_release_port(pi->eth_dev);
+ }
}
adapter->flags &= ~FULL_INIT_DONE;
}
@@ -1265,21 +1270,16 @@ int cxgbe_probe(struct adapter *adapter)
}
for_each_port(adapter, i) {
- char name[RTE_ETH_NAME_MAX_LEN];
- struct rte_eth_dev_data *data = NULL;
const unsigned int numa_node = rte_socket_id();
+ char name[RTE_ETH_NAME_MAX_LEN];
+ struct rte_eth_dev *eth_dev;
- pi = &adapter->port[i];
- pi->adapter = adapter;
- pi->xact_addr_filt = -1;
- pi->port_id = i;
-
- snprintf(name, sizeof(name), "cxgbe%d",
- adapter->eth_dev->data->port_id + i);
+ snprintf(name, sizeof(name), "%s_%d",
+ adapter->pdev->device.name, i);
if (i == 0) {
/* First port is already allocated by DPDK */
- pi->eth_dev = adapter->eth_dev;
+ eth_dev = adapter->eth_dev;
goto allocate_mac;
}
@@ -1289,21 +1289,25 @@ int cxgbe_probe(struct adapter *adapter)
*/
/* reserve an ethdev entry */
- pi->eth_dev = rte_eth_dev_allocate(name);
- if (!pi->eth_dev)
+ eth_dev = rte_eth_dev_allocate(name);
+ if (!eth_dev)
goto out_free;
- data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);
- if (!data)
+ eth_dev->data->dev_private =
+ rte_zmalloc_socket(name, sizeof(struct port_info),
+ RTE_CACHE_LINE_SIZE, numa_node);
+ if (!eth_dev->data->dev_private)
goto out_free;
- data->port_id = adapter->eth_dev->data->port_id + i;
-
- pi->eth_dev->data = data;
-
allocate_mac:
+ pi = (struct port_info *)eth_dev->data->dev_private;
+ adapter->port[i] = pi;
+ pi->eth_dev = eth_dev;
+ pi->adapter = adapter;
+ pi->xact_addr_filt = -1;
+ pi->port_id = i;
+
pi->eth_dev->device = &adapter->pdev->device;
- pi->eth_dev->data->dev_private = pi;
pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
@@ -1349,8 +1353,11 @@ int cxgbe_probe(struct adapter *adapter)
/* Skip first port since it'll be de-allocated by DPDK */
if (i == 0)
continue;
- if (pi->eth_dev->data)
- rte_free(pi->eth_dev->data);
+ if (pi->eth_dev) {
+ if (pi->eth_dev->data->dev_private)
+ rte_free(pi->eth_dev->data->dev_private);
+ rte_eth_dev_release_port(pi->eth_dev);
+ }
}
if (adapter->flags & FW_OK)
--
2.14.1
next prev parent reply other threads:[~2018-02-28 18:05 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-04 6:06 [dpdk-dev] [PATCH 0/7] cxgbe: bug fixes and updates Rahul Lakkireddy
2018-02-04 6:06 ` [dpdk-dev] [PATCH 1/7] cxgbe: fix secondary process initialization Rahul Lakkireddy
2018-02-05 17:23 ` Ferruh Yigit
2018-02-06 9:20 ` Rahul Lakkireddy
2018-02-04 6:06 ` [dpdk-dev] [PATCH 2/7] cxgbe: update link state when link speed changes Rahul Lakkireddy
2018-02-05 17:05 ` Ferruh Yigit
2018-02-04 6:06 ` [dpdk-dev] [PATCH 3/7] cxgbe: add support to update RSS hash configuration and key Rahul Lakkireddy
2018-02-05 17:09 ` Ferruh Yigit
2018-02-06 9:22 ` Rahul Lakkireddy
2018-02-06 10:11 ` Ferruh Yigit
2018-02-06 10:38 ` Thomas Monjalon
2018-02-07 7:01 ` Rahul Lakkireddy
2018-02-04 6:06 ` [dpdk-dev] [PATCH 4/7] cxgbe: add support to get programmed " Rahul Lakkireddy
2018-02-04 6:06 ` [dpdk-dev] [PATCH 5/7] cxgbe: update link Forward Error Correction (FEC) Rahul Lakkireddy
2018-02-04 6:06 ` [dpdk-dev] [PATCH 6/7] cxgbe: update link configuration for 32-bit port capability Rahul Lakkireddy
2018-02-04 6:06 ` [dpdk-dev] [PATCH 7/7] cxgbe: rework and use " Rahul Lakkireddy
2018-02-28 18:04 ` [dpdk-dev] [PATCH v2 0/7] cxgbe: bug fixes and updates Rahul Lakkireddy
2018-02-28 18:04 ` Rahul Lakkireddy [this message]
2018-02-28 18:04 ` [dpdk-dev] [PATCH v2 2/7] cxgbe: fix secondary process initialization Rahul Lakkireddy
2018-02-28 18:04 ` [dpdk-dev] [PATCH v2 3/7] cxgbe: add support to update RSS hash configuration and key Rahul Lakkireddy
2018-03-08 13:34 ` Ferruh Yigit
2018-03-10 5:21 ` Rahul Lakkireddy
2018-02-28 18:04 ` [dpdk-dev] [PATCH v2 4/7] cxgbe: add support to get programmed " Rahul Lakkireddy
2018-02-28 18:04 ` [dpdk-dev] [PATCH v2 5/7] cxgbe: update link Forward Error Correction (FEC) Rahul Lakkireddy
2018-02-28 18:04 ` [dpdk-dev] [PATCH v2 6/7] cxgbe: update link configuration for 32-bit port capability Rahul Lakkireddy
2018-02-28 18:04 ` [dpdk-dev] [PATCH v2 7/7] cxgbe: rework and use " Rahul Lakkireddy
2018-03-08 13:44 ` [dpdk-dev] [PATCH v2 0/7] cxgbe: bug fixes and updates Ferruh Yigit
2018-03-08 13:50 ` Ferruh Yigit
2018-03-10 5:24 ` Rahul Lakkireddy
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