From: "lihuisong (C)" <lihuisong@huawei.com>
To: Jie Hai <haijie1@huawei.com>, <dev@dpdk.org>,
Yisen Zhuang <yisen.zhuang@huawei.com>
Cc: <fengchengwen@huawei.com>
Subject: Re: [PATCH v5 5/7] net/hns3: add names for registers
Date: Fri, 8 Mar 2024 17:41:45 +0800 [thread overview]
Message-ID: <9eb108ac-d6e8-1281-5a3a-8b2cf7721266@huawei.com> (raw)
In-Reply-To: <20240307030247.599394-6-haijie1@huawei.com>
Reviewed-by: Huisong Li <lihuisong@huawei.com>
在 2024/3/7 11:02, Jie Hai 写道:
> This patch adds names for all registers to be dumped.
> For those who can be directly accessed by their addresses,
> a new structure containing both name and address is added
> and the related arrays is refactored and renamed.
>
> For the remaining modules, there may be different meanings
> on different platforms for the same field. Therefore, two
> name fields are provided.
>
> There are some 64-bit registers, dump them as two 32-bit
> registers.
>
> Signed-off-by: Jie Hai <haijie1@huawei.com>
> ---
> drivers/net/hns3/hns3_regs.c | 877 ++++++++++++++++++++++++++++++++---
> 1 file changed, 801 insertions(+), 76 deletions(-)
>
> diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c
> index b1c0d538a3c8..b7e4f78eecde 100644
> --- a/drivers/net/hns3/hns3_regs.c
> +++ b/drivers/net/hns3/hns3_regs.c
> @@ -14,67 +14,84 @@
>
> static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count);
>
> -static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
> - HNS3_CMDQ_TX_ADDR_H_REG,
> - HNS3_CMDQ_TX_DEPTH_REG,
> - HNS3_CMDQ_TX_TAIL_REG,
> - HNS3_CMDQ_TX_HEAD_REG,
> - HNS3_CMDQ_RX_ADDR_L_REG,
> - HNS3_CMDQ_RX_ADDR_H_REG,
> - HNS3_CMDQ_RX_DEPTH_REG,
> - HNS3_CMDQ_RX_TAIL_REG,
> - HNS3_CMDQ_RX_HEAD_REG,
> - HNS3_VECTOR0_CMDQ_SRC_REG,
> - HNS3_CMDQ_INTR_STS_REG,
> - HNS3_CMDQ_INTR_EN_REG,
> - HNS3_CMDQ_INTR_GEN_REG};
> -
> -static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
> - HNS3_VECTOR0_OTER_EN_REG,
> - HNS3_MISC_RESET_STS_REG,
> - HNS3_VECTOR0_OTHER_INT_STS_REG,
> - HNS3_GLOBAL_RESET_REG,
> - HNS3_FUN_RST_ING,
> - HNS3_GRO_EN_REG};
> -
> -static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
> - HNS3_FUN_RST_ING,
> - HNS3_GRO_EN_REG};
> -
> -static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
> - HNS3_RING_RX_BASEADDR_H_REG,
> - HNS3_RING_RX_BD_NUM_REG,
> - HNS3_RING_RX_BD_LEN_REG,
> - HNS3_RING_RX_EN_REG,
> - HNS3_RING_RX_MERGE_EN_REG,
> - HNS3_RING_RX_TAIL_REG,
> - HNS3_RING_RX_HEAD_REG,
> - HNS3_RING_RX_FBDNUM_REG,
> - HNS3_RING_RX_OFFSET_REG,
> - HNS3_RING_RX_FBD_OFFSET_REG,
> - HNS3_RING_RX_STASH_REG,
> - HNS3_RING_RX_BD_ERR_REG,
> - HNS3_RING_TX_BASEADDR_L_REG,
> - HNS3_RING_TX_BASEADDR_H_REG,
> - HNS3_RING_TX_BD_NUM_REG,
> - HNS3_RING_TX_EN_REG,
> - HNS3_RING_TX_PRIORITY_REG,
> - HNS3_RING_TX_TC_REG,
> - HNS3_RING_TX_MERGE_EN_REG,
> - HNS3_RING_TX_TAIL_REG,
> - HNS3_RING_TX_HEAD_REG,
> - HNS3_RING_TX_FBDNUM_REG,
> - HNS3_RING_TX_OFFSET_REG,
> - HNS3_RING_TX_EBD_NUM_REG,
> - HNS3_RING_TX_EBD_OFFSET_REG,
> - HNS3_RING_TX_BD_ERR_REG,
> - HNS3_RING_EN_REG};
> -
> -static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
> - HNS3_TQP_INTR_GL0_REG,
> - HNS3_TQP_INTR_GL1_REG,
> - HNS3_TQP_INTR_GL2_REG,
> - HNS3_TQP_INTR_RL_REG};
> +struct direct_reg_list {
> + const char *name;
> + uint32_t addr;
> +};
> +
> +#define STR(s) #s
> +
> +static const struct direct_reg_list cmdq_reg_list[] = {
> + {STR(HNS3_CMDQ_TX_ADDR_L_REG), HNS3_CMDQ_TX_ADDR_L_REG},
> + {STR(HNS3_CMDQ_TX_ADDR_H_REG), HNS3_CMDQ_TX_ADDR_H_REG},
> + {STR(HNS3_CMDQ_TX_DEPTH_REG), HNS3_CMDQ_TX_DEPTH_REG},
> + {STR(HNS3_CMDQ_TX_TAIL_REG), HNS3_CMDQ_TX_TAIL_REG},
> + {STR(HNS3_CMDQ_TX_HEAD_REG), HNS3_CMDQ_TX_HEAD_REG},
> + {STR(HNS3_CMDQ_RX_ADDR_L_REG), HNS3_CMDQ_RX_ADDR_L_REG},
> + {STR(HNS3_CMDQ_RX_ADDR_H_REG), HNS3_CMDQ_RX_ADDR_H_REG},
> + {STR(HNS3_CMDQ_RX_DEPTH_REG), HNS3_CMDQ_RX_DEPTH_REG},
> + {STR(HNS3_CMDQ_RX_TAIL_REG), HNS3_CMDQ_RX_TAIL_REG},
> + {STR(HNS3_CMDQ_RX_HEAD_REG), HNS3_CMDQ_RX_HEAD_REG},
> + {STR(HNS3_VECTOR0_CMDQ_SRC_REG), HNS3_VECTOR0_CMDQ_SRC_REG},
> + {STR(HNS3_CMDQ_INTR_STS_REG), HNS3_CMDQ_INTR_STS_REG},
> + {STR(HNS3_CMDQ_INTR_EN_REG), HNS3_CMDQ_INTR_EN_REG},
> + {STR(HNS3_CMDQ_INTR_GEN_REG), HNS3_CMDQ_INTR_GEN_REG},
> +};
> +
> +static const struct direct_reg_list common_reg_list[] = {
> + {STR(HNS3_MISC_VECTOR_REG_BASE), HNS3_MISC_VECTOR_REG_BASE},
> + {STR(HNS3_VECTOR0_OTER_EN_REG), HNS3_VECTOR0_OTER_EN_REG},
> + {STR(HNS3_MISC_RESET_STS_REG), HNS3_MISC_RESET_STS_REG},
> + {STR(HNS3_VECTOR0_OTHER_INT_STS_REG), HNS3_VECTOR0_OTHER_INT_STS_REG},
> + {STR(HNS3_GLOBAL_RESET_REG), HNS3_GLOBAL_RESET_REG},
> + {STR(HNS3_FUN_RST_ING), HNS3_FUN_RST_ING},
> + {STR(HNS3_GRO_EN_REG), HNS3_GRO_EN_REG},
> +};
> +
> +static const struct direct_reg_list common_vf_reg_list[] = {
> + {STR(HNS3_MISC_VECTOR_REG_BASE), HNS3_MISC_VECTOR_REG_BASE},
> + {STR(HNS3_FUN_RST_ING), HNS3_FUN_RST_ING},
> + {STR(HNS3_GRO_EN_REG), HNS3_GRO_EN_REG},
> +};
> +
> +static const struct direct_reg_list ring_reg_list[] = {
> + {STR(HNS3_RING_RX_BASEADDR_L_REG), HNS3_RING_RX_BASEADDR_L_REG},
> + {STR(HNS3_RING_RX_BASEADDR_H_REG), HNS3_RING_RX_BASEADDR_H_REG},
> + {STR(HNS3_RING_RX_BD_NUM_REG), HNS3_RING_RX_BD_NUM_REG},
> + {STR(HNS3_RING_RX_BD_LEN_REG), HNS3_RING_RX_BD_LEN_REG},
> + {STR(HNS3_RING_RX_EN_REG), HNS3_RING_RX_EN_REG},
> + {STR(HNS3_RING_RX_MERGE_EN_REG), HNS3_RING_RX_MERGE_EN_REG},
> + {STR(HNS3_RING_RX_TAIL_REG), HNS3_RING_RX_TAIL_REG},
> + {STR(HNS3_RING_RX_HEAD_REG), HNS3_RING_RX_HEAD_REG},
> + {STR(HNS3_RING_RX_FBDNUM_REG), HNS3_RING_RX_FBDNUM_REG},
> + {STR(HNS3_RING_RX_OFFSET_REG), HNS3_RING_RX_OFFSET_REG},
> + {STR(HNS3_RING_RX_FBD_OFFSET_REG), HNS3_RING_RX_FBD_OFFSET_REG},
> + {STR(HNS3_RING_RX_STASH_REG), HNS3_RING_RX_STASH_REG},
> + {STR(HNS3_RING_RX_BD_ERR_REG), HNS3_RING_RX_BD_ERR_REG},
> + {STR(HNS3_RING_TX_BASEADDR_L_REG), HNS3_RING_TX_BASEADDR_L_REG},
> + {STR(HNS3_RING_TX_BASEADDR_H_REG), HNS3_RING_TX_BASEADDR_H_REG},
> + {STR(HNS3_RING_TX_BD_NUM_REG), HNS3_RING_TX_BD_NUM_REG},
> + {STR(HNS3_RING_TX_EN_REG), HNS3_RING_TX_EN_REG},
> + {STR(HNS3_RING_TX_PRIORITY_REG), HNS3_RING_TX_PRIORITY_REG},
> + {STR(HNS3_RING_TX_TC_REG), HNS3_RING_TX_TC_REG},
> + {STR(HNS3_RING_TX_MERGE_EN_REG), HNS3_RING_TX_MERGE_EN_REG},
> + {STR(HNS3_RING_TX_TAIL_REG), HNS3_RING_TX_TAIL_REG},
> + {STR(HNS3_RING_TX_HEAD_REG), HNS3_RING_TX_HEAD_REG},
> + {STR(HNS3_RING_TX_FBDNUM_REG), HNS3_RING_TX_FBDNUM_REG},
> + {STR(HNS3_RING_TX_OFFSET_REG), HNS3_RING_TX_OFFSET_REG},
> + {STR(HNS3_RING_TX_EBD_NUM_REG), HNS3_RING_TX_EBD_NUM_REG},
> + {STR(HNS3_RING_TX_EBD_OFFSET_REG), HNS3_RING_TX_EBD_OFFSET_REG},
> + {STR(HNS3_RING_TX_BD_ERR_REG), HNS3_RING_TX_BD_ERR_REG},
> + {STR(HNS3_RING_EN_REG), HNS3_RING_EN_REG},
> +};
> +
> +static const struct direct_reg_list tqp_intr_reg_list[] = {
> + {STR(HNS3_TQP_INTR_CTRL_REG), HNS3_TQP_INTR_CTRL_REG},
> + {STR(HNS3_TQP_INTR_GL0_REG), HNS3_TQP_INTR_GL0_REG},
> + {STR(HNS3_TQP_INTR_GL1_REG), HNS3_TQP_INTR_GL1_REG},
> + {STR(HNS3_TQP_INTR_GL2_REG), HNS3_TQP_INTR_GL2_REG},
> + {STR(HNS3_TQP_INTR_RL_REG), HNS3_TQP_INTR_RL_REG},
> +};
>
> static const uint32_t hns3_dfx_reg_opcode_list[] = {
> HNS3_OPC_DFX_BIOS_COMMON_REG,
> @@ -91,6 +108,708 @@ static const uint32_t hns3_dfx_reg_opcode_list[] = {
> HNS3_OPC_DFX_SSU_REG_2
> };
>
> +struct hns3_reg_entry {
> + const char *new_name;
> + const char *old_name;
> +};
> +
> +static struct hns3_reg_entry regs_32_bit_list[] = {
> + {"ssu_common_err_int"},
> + {"ssu_port_based_err_int"},
> + {"ssu_fifo_overflow_int"},
> + {"ssu_ets_tcg_int"},
> + {"ssu_bp_status_0"},
> + {"ssu_bp_status_1"},
> +
> + {"ssu_bp_status_2"},
> + {"ssu_bp_status_3"},
> + {"ssu_bp_status_4"},
> + {"ssu_bp_status_5"},
> + {"ssu_mac_tx_pfc_ind"},
> + {"ssu_mac_rx_pfc_ind"},
> +
> + {"ssu_rx_oq_drop_pkt_cnt"},
> + {"ssu_tx_oq_drop_pkt_cnt"},
> +};
> +
> +static struct hns3_reg_entry regs_64_bit_list[] = {
> + {"ppp_get_rx_pkt_cnt_l"},
> + {"ppp_get_rx_pkt_cnt_h"},
> + {"ppp_get_tx_pkt_cnt_l"},
> + {"ppp_get_tx_pkt_cnt_h"},
> + {"ppp_send_uc_prt2host_pkt_cnt_l"},
> + {"ppp_send_uc_prt2host_pkt_cnt_h"},
> +
> + {"ppp_send_uc_prt2prt_pkt_cnt_l"},
> + {"ppp_send_uc_prt2prt_pkt_cnt_h"},
> + {"ppp_send_uc_host2host_pkt_cnt_l"},
> + {"ppp_send_uc_host2host_pkt_cnt_h"},
> + {"ppp_send_uc_host2prt_pkt_cnt_l"},
> + {"ppp_send_uc_host2prt_pkt_cnt_h"},
> + {"ppp_send_mc_from_prt_cnt_l"},
> + {"ppp_send_mc_from_prt_cnt_h"},
> +};
> +
> +static struct hns3_reg_entry dfx_bios_common_reg_list[] = {
> + {"bios_rsv0"},
> + {"bp_cpu_state"},
> + {"dfx_msix_info_nic_0"},
> + {"dfx_msix_info_nic_1"},
> + {"dfx_msix_info_nic_2"},
> + {"dfx_msix_info_nic_3"},
> +
> + {"dfx_msix_info_roce_0"},
> + {"dfx_msix_info_roce_1"},
> + {"dfx_msix_info_roce_2"},
> + {"dfx_msix_info_roce_3"},
> + {"bios_rsv1"},
> + {"bios_rsv2"},
> +};
> +
> +static struct hns3_reg_entry dfx_ssu_reg_0_list[] = {
> + {"dfx_ssu0_rsv0"},
> + {"ssu_ets_port_status"},
> + {"ssu_ets_tcg_status"},
> + {"dfx_ssu0_rsv1"},
> + {"dfx_ssu0_rsv2"},
> + {"ssu_bp_status_0"},
> +
> + {"ssu_bp_status_1"},
> + {"ssu_bp_status_2"},
> + {"ssu_bp_status_3"},
> + {"ssu_bp_status_4"},
> + {"ssu_bp_status_5"},
> + {"ssu_mac_tx_pfc_ind"},
> +
> + {"mac_ssu_rx_pfc_ind"},
> + {"ssu_btmp_ageing_st_b0"},
> + {"ssu_btmp_ageing_st_b1"},
> + {"ssu_btmp_ageing_st_b2"},
> + {"dfx_ssu0_rsv3"},
> + {"dfx_ssu0_rsv4"},
> +
> + {"ssu_full_drop_num"},
> + {"ssu_part_drop_num"},
> + {"ppp_key_drop_num"},
> + {"ppp_rlt_drop_num"},
> + {"ssu_lo_pri_unicast_rlt_drop_num"},
> + {"ssu_hi_pri_multicast_rlt_drop_num"},
> +
> + {"ssu_lo_pri_multicast_rlt_drop_num"},
> + {"ssu_ncsi_packet_curr_buffer_cnt"},
> + {"dfx_ssu0_rsv5", "ssu_btmp_ageing_rls_cnt_bank0"},
> + {"dfx_ssu0_rsv6", "ssu_btmp_ageing_rls_cnt_bank1"},
> + {"dfx_ssu0_rsv7", "ssu_btmp_ageing_rls_cnt_bank2"},
> + {"ssu_mb_rd_rlt_drop_cnt"},
> +
> + {"ssu_ppp_mac_key_num_l"},
> + {"ssu_ppp_mac_key_num_h"},
> + {"ssu_ppp_host_key_num_l"},
> + {"ssu_ppp_host_key_num_h"},
> + {"ppp_ssu_mac_rlt_num_l"},
> + {"ppp_ssu_mac_rlt_num_h"},
> +
> + {"ppp_ssu_host_rlt_num_l"},
> + {"ppp_ssu_host_rlt_num_h"},
> + {"ssu_ncsi_rx_packet_in_cnt_l"},
> + {"ssu_ncsi_rx_packet_in_cnt_h"},
> + {"ssu_ncsi_tx_packet_out_cnt_l"},
> + {"ssu_ncsi_tx_packet_out_cnt_h"},
> +
> + {"ssu_key_drop_num"},
> + {"ssu_mb_uncopy_num"},
> + {"ssu_rx_oq_drop_pkt_cnt"},
> + {"ssu_tx_oq_drop_pkt_cnt"},
> + {"ssu_bank_unbalance_drop_cnt"},
> + {"ssu_bank_unbalance_rx_drop_cnt"},
> +
> + {"ssu_nic_l2_eer_drop_pkt_cnt"},
> + {"ssu_roc_l2_eer_drop_pkt_cnt"},
> + {"ssu_nic_l2_eer_drop_pkt_cnt_rx"},
> + {"ssu_roc_l2_eer_drop_pkt_cnt_rx"},
> + {"ssu_rx_oq_glb_drop_pkt_cnt"},
> + {"ssu_dfx_ssu0_rsv8"},
> +
> + {"ssu_lo_pri_unicast_cur_cnt"},
> + {"ssu_hi_pri_multicast_cur_cnt"},
> + {"ssu_lo_pri_multicast_cur_cnt"},
> + {"dfx_ssu0_rsv9"},
> + {"dfx_ssu0_rsv10"},
> + {"dfx_ssu0_rsv11"},
> +};
> +
> +static struct hns3_reg_entry dfx_ssu_reg_1_list[] = {
> + {"dfx_ssu1_prt_id"},
> + {"ssu_packet_tc_curr_buffer_cnt_0"},
> + {"ssu_packet_tc_curr_buffer_cnt_1"},
> + {"ssu_packet_tc_curr_buffer_cnt_2"},
> + {"ssu_packet_tc_curr_buffer_cnt_3"},
> + {"ssu_packet_tc_curr_buffer_cnt_4"},
> +
> + {"ssu_packet_tc_curr_buffer_cnt_5"},
> + {"ssu_packet_tc_curr_buffer_cnt_6"},
> + {"ssu_packet_tc_curr_buffer_cnt_7"},
> + {"ssu_packet_curr_buffer_cnt"},
> + {"dfx_ssu1_rsv0"},
> + {"dfx_ssu1_rsv1"},
> +
> + {"ssu_rx_packet_in_cnt_l"},
> + {"ssu_rx_packet_in_cnt_h"},
> + {"ssu_rx_packet_out_cnt_l"},
> + {"ssu_rx_packet_out_cnt_h"},
> + {"ssu_tx_packet_in_cnt_l"},
> + {"ssu_tx_packet_in_cnt_h"},
> +
> + {"ssu_tx_packet_out_cnt_l"},
> + {"ssu_tx_packet_out_cnt_h"},
> + {"ssu_roc_rx_packet_in_cnt_l"},
> + {"ssu_roc_rx_packet_in_cnt_h"},
> + {"ssu_roc_tx_packet_in_cnt_l"},
> + {"ssu_roc_tx_packet_in_cnt_h"},
> +
> + {"ssu_rx_packet_tc_in_cnt_0_l"},
> + {"ssu_rx_packet_tc_in_cnt_0_h"},
> + {"ssu_rx_packet_tc_in_cnt_1_l"},
> + {"ssu_rx_packet_tc_in_cnt_1_h"},
> + {"ssu_rx_packet_tc_in_cnt_2_l"},
> + {"ssu_rx_packet_tc_in_cnt_2_h"},
> +
> + {"ssu_rx_packet_tc_in_cnt_3_l"},
> + {"ssu_rx_packet_tc_in_cnt_3_h"},
> + {"ssu_rx_packet_tc_in_cnt_4_l"},
> + {"ssu_rx_packet_tc_in_cnt_4_h"},
> + {"ssu_rx_packet_tc_in_cnt_5_l"},
> + {"ssu_rx_packet_tc_in_cnt_5_h"},
> +
> + {"ssu_rx_packet_tc_in_cnt_6_l"},
> + {"ssu_rx_packet_tc_in_cnt_6_h"},
> + {"ssu_rx_packet_tc_in_cnt_7_l"},
> + {"ssu_rx_packet_tc_in_cnt_7_h"},
> + {"ssu_rx_packet_tc_out_cnt_0_l"},
> + {"ssu_rx_packet_tc_out_cnt_0_h"},
> +
> + {"ssu_rx_packet_tc_out_cnt_1_l"},
> + {"ssu_rx_packet_tc_out_cnt_1_h"},
> + {"ssu_rx_packet_tc_out_cnt_2_l"},
> + {"ssu_rx_packet_tc_out_cnt_2_h"},
> + {"ssu_rx_packet_tc_out_cnt_3_l"},
> + {"ssu_rx_packet_tc_out_cnt_3_h"},
> +
> + {"ssu_rx_packet_tc_out_cnt_4_l"},
> + {"ssu_rx_packet_tc_out_cnt_4_h"},
> + {"ssu_rx_packet_tc_out_cnt_5_l"},
> + {"ssu_rx_packet_tc_out_cnt_5_h"},
> + {"ssu_rx_packet_tc_out_cnt_6_l"},
> + {"ssu_rx_packet_tc_out_cnt_6_h"},
> +
> + {"ssu_rx_packet_tc_out_cnt_7_l"},
> + {"ssu_rx_packet_tc_out_cnt_7_h"},
> + {"ssu_tx_packet_tc_in_cnt_0_l"},
> + {"ssu_tx_packet_tc_in_cnt_0_h"},
> + {"ssu_tx_packet_tc_in_cnt_1_l"},
> + {"ssu_tx_packet_tc_in_cnt_1_h"},
> +
> + {"ssu_tx_packet_tc_in_cnt_2_l"},
> + {"ssu_tx_packet_tc_in_cnt_2_h"},
> + {"ssu_tx_packet_tc_in_cnt_3_l"},
> + {"ssu_tx_packet_tc_in_cnt_3_h"},
> + {"ssu_tx_packet_tc_in_cnt_4_l"},
> + {"ssu_tx_packet_tc_in_cnt_4_h"},
> +
> + {"ssu_tx_packet_tc_in_cnt_5_l"},
> + {"ssu_tx_packet_tc_in_cnt_5_h"},
> + {"ssu_tx_packet_tc_in_cnt_6_l"},
> + {"ssu_tx_packet_tc_in_cnt_6_h"},
> + {"ssu_tx_packet_tc_in_cnt_7_l"},
> + {"ssu_tx_packet_tc_in_cnt_7_h"},
> +
> + {"ssu_tx_packet_tc_out_cnt_0_l"},
> + {"ssu_tx_packet_tc_out_cnt_0_h"},
> + {"ssu_tx_packet_tc_out_cnt_1_l"},
> + {"ssu_tx_packet_tc_out_cnt_1_h"},
> + {"ssu_tx_packet_tc_out_cnt_2_l"},
> + {"ssu_tx_packet_tc_out_cnt_2_h"},
> +
> + {"ssu_tx_packet_tc_out_cnt_3_l"},
> + {"ssu_tx_packet_tc_out_cnt_3_h"},
> + {"ssu_tx_packet_tc_out_cnt_4_l"},
> + {"ssu_tx_packet_tc_out_cnt_4_h"},
> + {"ssu_tx_packet_tc_out_cnt_5_l"},
> + {"ssu_tx_packet_tc_out_cnt_5_h"},
> +
> + {"ssu_tx_packet_tc_out_cnt_6_l"},
> + {"ssu_tx_packet_tc_out_cnt_6_h"},
> + {"ssu_tx_packet_tc_out_cnt_7_l"},
> + {"ssu_tx_packet_tc_out_cnt_7_h"},
> + {"dfx_ssu1_rsv2"},
> + {"dfx_ssu1_rsv3"},
> +};
> +
> +static struct hns3_reg_entry dfx_igu_egu_reg_list[] = {
> + {"igu_egu_prt_id"},
> + {"igu_rx_err_pkt"},
> + {"igu_rx_no_sof_pkt"},
> + {"egu_tx_1588_short_pkt"},
> + {"egu_tx_1588_pkt"},
> + {"egu_tx_1588_err_pkt"},
> +
> + {"igu_rx_out_l2_pkt"},
> + {"igu_rx_out_l3_pkt"},
> + {"igu_rx_out_l4_pkt"},
> + {"igu_rx_in_l2_pkt"},
> + {"igu_rx_in_l3_pkt"},
> + {"igu_rx_in_l4_pkt"},
> +
> + {"igu_rx_el3e_pkt"},
> + {"igu_rx_el4e_pkt"},
> + {"igu_rx_l3e_pkt"},
> + {"igu_rx_l4e_pkt"},
> + {"igu_rx_rocee_pkt"},
> + {"igu_rx_out_udp0_pkt"},
> +
> + {"igu_rx_in_udp0_pkt"},
> + {"igu_egu_mul_car_drop_pkt_cnt_l", "igu_egu_rsv0"},
> + {"igu_egu_mul_car_drop_pkt_cnt_h", "igu_egu_rsv1"},
> + {"igu_egu_bro_car_drop_pkt_cnt_l", "igu_egu_rsv2"},
> + {"igu_egu_bro_car_drop_pkt_cnt_h", "igu_egu_rsv3"},
> + {"igu_egu_rsv0", "igu_egu_rsv4"},
> +
> + {"igu_rx_oversize_pkt_l"},
> + {"igu_rx_oversize_pkt_h"},
> + {"igu_rx_undersize_pkt_l"},
> + {"igu_rx_undersize_pkt_h"},
> + {"igu_rx_out_all_pkt_l"},
> + {"igu_rx_out_all_pkt_h"},
> +
> + {"igu_tx_out_all_pkt_l"},
> + {"igu_tx_out_all_pkt_h"},
> + {"igu_rx_uni_pkt_l"},
> + {"igu_rx_uni_pkt_h"},
> + {"igu_rx_multi_pkt_l"},
> + {"igu_rx_multi_pkt_h"},
> +
> + {"igu_rx_broad_pkt_l"},
> + {"igu_rx_broad_pkt_h"},
> + {"egu_tx_out_all_pkt_l"},
> + {"egu_tx_out_all_pkt_h"},
> + {"egu_tx_uni_pkt_l"},
> + {"egu_tx_uni_pkt_h"},
> +
> + {"egu_tx_multi_pkt_l"},
> + {"egu_tx_multi_pkt_h"},
> + {"egu_tx_broad_pkt_l"},
> + {"egu_tx_broad_pkt_h"},
> + {"igu_tx_key_num_l"},
> + {"igu_tx_key_num_h"},
> +
> + {"igu_rx_non_tun_pkt_l"},
> + {"igu_rx_non_tun_pkt_h"},
> + {"igu_rx_tun_pkt_l"},
> + {"igu_rx_tun_pkt_h"},
> + {"igu_egu_rsv5"},
> + {"igu_egu_rsv6"},
> +};
> +
> +static struct hns3_reg_entry dfx_rpu_reg_0_list[] = {
> + {"rpu_currport_tnl_index", "rpu_tc_queue_num"},
> + {"rpu_fsm_dfx_st0"},
> + {"rpu_fsm_dfx_st1"},
> + {"rpu_rpu_rx_pkt_drop_cnt"},
> + {"rpu_buf_wait_timeout"},
> + {"rpu_buf_wait_timeout_qid"},
> +};
> +
> +static struct hns3_reg_entry dfx_rpu_reg_1_list[] = {
> + {"rpu_rsv0"},
> + {"rpu_fifo_dfx_st0"},
> + {"rpu_fifo_dfx_st1"},
> + {"rpu_fifo_dfx_st2"},
> + {"rpu_fifo_dfx_st3"},
> + {"rpu_fifo_dfx_st4"},
> +
> + {"rpu_fifo_dfx_st5"},
> + {"rpu_rsv1"},
> + {"rpu_rsv2"},
> + {"rpu_rsv3"},
> + {"rpu_rsv4"},
> + {"rpu_rsv5"},
> +};
> +
> +static struct hns3_reg_entry dfx_ncsi_reg_list[] = {
> + {"ncsi_rsv0"},
> + {"ncsi_egu_tx_fifo_sts"},
> + {"ncsi_pause_status"},
> + {"ncsi_rx_ctrl_dmac_err_cnt"},
> + {"ncsi_rx_ctrl_smac_err_cnt"},
> + {"ncsi_rx_ctrl_cks_err_cnt"},
> +
> + {"ncsi_rx_ctrl_pkt_err_cnt"},
> + {"ncsi_rx_pt_dmac_err_cnt"},
> + {"ncsi_rx_pt_smac_err_cnt"},
> + {"ncsi_rx_pt_pkt_cnt"},
> + {"ncsi_rx_fcs_err_cnt"},
> + {"ncsi_tx_ctrl_dmac_err_cnt"},
> +
> + {"ncsi_tx_ctrl_smac_err_cnt"},
> + {"ncsi_tx_ctrl_pkt_cnt"},
> + {"ncsi_tx_pt_dmac_err_cnt"},
> + {"ncsi_tx_pt_smac_err_cnt"},
> + {"ncsi_tx_pt_pkt_cnt"},
> + {"ncsi_tx_pt_pkt_trun_cnt"},
> +
> + {"ncsi_tx_pt_pkt_err_cnt"},
> + {"ncsi_tx_ctrl_pkt_err_cnt"},
> + {"ncsi_rx_ctrl_pkt_trun_cnt"},
> + {"ncsi_rx_ctrl_pkt_cflit_cnt"},
> + {"ncsi_rsv1"},
> + {"ncsi_rsv2"},
> +
> + {"ncsi_mac_rx_octets_ok"},
> + {"ncsi_mac_rx_octets_bad"},
> + {"ncsi_mac_rx_uc_pkts"},
> + {"ncsi_mac_rx_mc_pkts"},
> + {"ncsi_mac_rx_bc_pkts"},
> + {"ncsi_mac_rx_pkts_64octets"},
> +
> + {"ncsi_mac_rx_pkts_64to127_octets"},
> + {"ncsi_mac_rx_pkts_128to255_octets"},
> + {"ncsi_mac_rx_pkts_256to511_octets"},
> + {"ncsi_mac_rx_pkts_512to1023_octets"},
> + {"ncsi_mac_rx_pkts_1024to1518_octets"},
> + {"ncsi_mac_rx_pkts_1519tomax_octets"},
> +
> + {"ncsi_mac_rx_fcs_errors"},
> + {"ncsi_mac_rx_long_errors"},
> + {"ncsi_mac_rx_jabber_errors"},
> + {"ncsi_mac_rx_runt_err_cnt"},
> + {"ncsi_mac_rx_short_err_cnt"},
> + {"ncsi_mac_rx_filt_pkt_cnt"},
> +
> + {"ncsi_mac_rx_octets_total_filt"},
> + {"ncsi_mac_tx_octets_ok"},
> + {"ncsi_mac_tx_octets_bad"},
> + {"ncsi_mac_tx_uc_pkts"},
> + {"ncsi_mac_tx_mc_pkts"},
> + {"ncsi_mac_tx_bc_pkts"},
> +
> + {"ncsi_mac_tx_pkts_64octets"},
> + {"ncsi_mac_tx_pkts_64to127_octets"},
> + {"ncsi_mac_tx_pkts_128to255_octets"},
> + {"ncsi_mac_tx_pkts_256to511_octets"},
> + {"ncsi_mac_tx_pkts_512to1023_octets"},
> + {"ncsi_mac_tx_pkts_1024to1518_octets"},
> +
> + {"ncsi_mac_tx_pkts_1519tomax_octets"},
> + {"ncsi_mac_tx_underrun"},
> + {"ncsi_mac_tx_crc_error"},
> + {"ncsi_mac_tx_pause_frames"},
> + {"ncsi_mac_rx_pad_pkts"},
> + {"ncsi_mac_rx_pause_frames"},
> +};
> +
> +static struct hns3_reg_entry dfx_rtc_reg_list[] = {
> + {"rtc_rsv0"},
> + {"lge_igu_afifo_dfx_0"},
> + {"lge_igu_afifo_dfx_1"},
> + {"lge_igu_afifo_dfx_2"},
> + {"lge_igu_afifo_dfx_3"},
> + {"lge_igu_afifo_dfx_4"},
> +
> + {"lge_igu_afifo_dfx_5"},
> + {"lge_igu_afifo_dfx_6"},
> + {"lge_igu_afifo_dfx_7"},
> + {"lge_egu_afifo_dfx_0"},
> + {"lge_egu_afifo_dfx_1"},
> + {"lge_egu_afifo_dfx_2"},
> +
> + {"lge_egu_afifo_dfx_3"},
> + {"lge_egu_afifo_dfx_4"},
> + {"lge_egu_afifo_dfx_5"},
> + {"lge_egu_afifo_dfx_6"},
> + {"lge_egu_afifo_dfx_7"},
> + {"cge_igu_afifo_dfx_0"},
> +
> + {"cge_igu_afifo_dfx_1"},
> + {"cge_egu_afifo_dfx_0"},
> + {"cge_egu_afifo_dfx_i"},
> + {"rtc_rsv1"},
> + {"rtc_rsv2"},
> + {"rtc_rsv3"},
> +};
> +
> +static struct hns3_reg_entry dfx_ppp_reg_list[] = {
> + {"ppp_rsv0"},
> + {"ppp_drop_from_prt_pkt_cnt"},
> + {"ppp_drop_from_host_pkt_cnt"},
> + {"ppp_drop_tx_vlan_proc_cnt"},
> + {"ppp_drop_mng_cnt"},
> + {"ppp_drop_fd_cnt"},
> +
> + {"ppp_drop_no_dst_cnt"},
> + {"ppp_drop_mc_mbid_full_cnt"},
> + {"ppp_drop_sc_filtered"},
> + {"ppp_ppp_mc_drop_pkt_cnt"},
> + {"ppp_drop_pt_cnt"},
> + {"ppp_drop_mac_anti_spoof_cnt"},
> +
> + {"ppp_drop_ig_vfv_cnt"},
> + {"ppp_drop_ig_prtv_cnt"},
> + {"ppp_drop_cnm_pfc_pause_cnt"},
> + {"ppp_drop_torus_tc_cnt"},
> + {"ppp_drop_torus_lpbk_cnt"},
> + {"ppp_ppp_hfs_sts"},
> +
> + {"ppp_mc_rslt_sts"},
> + {"ppp_p3u_sts"},
> + {"ppp_rsv1", "ppp_rslt_descr_sts"},
> + {"ppp_umv_sts_0"},
> + {"ppp_umv_sts_1"},
> + {"ppp_vfv_sts"},
> +
> + {"ppp_gro_key_cnt"},
> + {"ppp_gro_info_cnt"},
> + {"ppp_gro_drop_cnt"},
> + {"ppp_gro_out_cnt"},
> + {"ppp_gro_key_match_data_cnt"},
> + {"ppp_gro_key_match_tcam_cnt"},
> +
> + {"ppp_gro_info_match_cnt"},
> + {"ppp_gro_free_entry_cnt"},
> + {"ppp_gro_inner_dfx_signal"},
> + {"ppp_rsv2"},
> + {"ppp_rsv3"},
> + {"ppp_rsv4"},
> +
> + {"ppp_get_rx_pkt_cnt_l"},
> + {"ppp_get_rx_pkt_cnt_h"},
> + {"ppp_get_tx_pkt_cnt_l"},
> + {"ppp_get_tx_pkt_cnt_h"},
> + {"ppp_send_uc_prt2host_pkt_cnt_l"},
> + {"ppp_send_uc_prt2host_pkt_cnt_h"},
> +
> + {"ppp_send_uc_prt2prt_pkt_cnt_l"},
> + {"ppp_send_uc_prt2prt_pkt_cnt_h"},
> + {"ppp_send_uc_host2host_pkt_cnt_l"},
> + {"ppp_send_uc_host2host_pkt_cnt_h"},
> + {"ppp_send_uc_host2prt_pkt_cnt_l"},
> + {"ppp_send_uc_host2prt_pkt_cnt_h"},
> +
> + {"ppp_send_mc_from_prt_cnt_l"},
> + {"ppp_send_mc_from_prt_cnt_h"},
> + {"ppp_send_mc_from_host_cnt_l"},
> + {"ppp_send_mc_from_host_cnt_h"},
> + {"ppp_ssu_mc_rd_cnt_l"},
> + {"ppp_ssu_mc_rd_cnt_h"},
> +
> + {"ppp_ssu_mc_drop_cnt_l"},
> + {"ppp_ssu_mc_drop_cnt_h"},
> + {"ppp_ssu_mc_rd_pkt_cnt_l"},
> + {"ppp_ssu_mc_rd_pkt_cnt_h"},
> + {"ppp_mc_2host_pkt_cnt_l"},
> + {"ppp_mc_2host_pkt_cnt_h"},
> +
> + {"ppp_mc_2prt_pkt_cnt_l"},
> + {"ppp_mc_2prt_pkt_cnt_h"},
> + {"ppp_ntsnos_pkt_cnt_l"},
> + {"ppp_ntsnos_pkt_cnt_h"},
> + {"ppp_ntup_pkt_cnt_l"},
> + {"ppp_ntup_pkt_cnt_h"},
> +
> + {"ppp_ntlcl_pkt_cnt_l"},
> + {"ppp_ntlcl_pkt_cnt_h"},
> + {"ppp_nttgt_pkt_cnt_l"},
> + {"ppp_nttgt_pkt_cnt_h"},
> + {"ppp_rtns_pkt_cnt_l"},
> + {"ppp_rtns_pkt_cnt_h"},
> +
> + {"ppp_rtlpbk_pkt_cnt_l"},
> + {"ppp_rtlpbk_pkt_cnt_h"},
> + {"ppp_nr_pkt_cnt_l"},
> + {"ppp_nr_pkt_cnt_h"},
> + {"ppp_rr_pkt_cnt_l"},
> + {"ppp_rr_pkt_cnt_h"},
> +
> + {"ppp_mng_tbl_hit_cnt_l"},
> + {"ppp_mng_tbl_hit_cnt_h"},
> + {"ppp_fd_tbl_hit_cnt_l"},
> + {"ppp_fd_tbl_hit_cnt_h"},
> + {"ppp_fd_lkup_cnt_l"},
> + {"ppp_fd_lkup_cnt_h"},
> +
> + {"ppp_bc_hit_cnt"},
> + {"ppp_bc_hit_cnt_h"},
> + {"ppp_um_tbl_uc_hit_cnt"},
> + {"ppp_um_tbl_uc_hit_cnt_h"},
> + {"ppp_um_tbl_mc_hit_cnt"},
> + {"ppp_um_tbl_mc_hit_cnt_h"},
> +
> + {"ppp_um_tbl_snq_hit_cnt_l", "ppp_um_tbl_vmdq1_hit_cnt_l"},
> + {"ppp_um_tbl_snq_hit_cnt_h", "ppp_um_tbl_vmdq1_hit_cnt_h"},
> + {"ppp_rsv5", "ppp_mta_tbl_hit_cnt_l"},
> + {"ppp_rsv6", "ppp_mta_tbl_hit_cnt_h"},
> + {"ppp_fwd_bonding_hit_cnt_l"},
> + {"ppp_fwd_bonding_hit_cnt_h"},
> +
> + {"ppp_promisc_tbl_hit_cnt_l"},
> + {"ppp_promisc_tbl_hit_cnt_h"},
> + {"ppp_get_tunl_pkt_cnt_l"},
> + {"ppp_get_tunl_pkt_cnt_h"},
> + {"ppp_get_bmc_pkt_cnt_l"},
> + {"ppp_get_bmc_pkt_cnt_h"},
> +
> + {"ppp_send_uc_prt2bmc_pkt_cnt_l"},
> + {"ppp_send_uc_prt2bmc_pkt_cnt_h"},
> + {"ppp_send_uc_host2bmc_pkt_cnt_l"},
> + {"ppp_send_uc_host2bmc_pkt_cnt_h"},
> + {"ppp_send_uc_bmc2host_pkt_cnt_l"},
> + {"ppp_send_uc_bmc2host_pkt_cnt_h"},
> +
> + {"ppp_send_uc_bmc2prt_pkt_cnt_l"},
> + {"ppp_send_uc_bmc2prt_pkt_cnt_h"},
> + {"ppp_mc_2bmc_pkt_cnt_l"},
> + {"ppp_mc_2bmc_pkt_cnt_h"},
> + {"ppp_rsv7", "ppp_vlan_mirr_cnt_l"},
> + {"ppp_rsv8", "ppp_vlan_mirr_cnt_h"},
> +
> + {"ppp_rsv9", "ppp_ig_mirr_cnt_l"},
> + {"ppp_rsv10", "ppp_ig_mirr_cnt_h"},
> + {"ppp_rsv11", "ppp_eg_mirr_cnt_l"},
> + {"ppp_rsv12", "ppp_eg_mirr_cnt_h"},
> + {"ppp_rx_default_host_hit_cnt_l"},
> + {"ppp_rx_default_host_hit_cnt_h"},
> +
> + {"ppp_lan_pair_cnt_l"},
> + {"ppp_lan_pair_cnt_h"},
> + {"ppp_um_tbl_mc_hit_pkt_cnt_l"},
> + {"ppp_um_tbl_mc_hit_pkt_cnt_h"},
> + {"ppp_mta_tbl_hit_pkt_cnt_l"},
> + {"ppp_mta_tbl_hit_pkt_cnt_h"},
> +
> + {"ppp_promisc_tbl_hit_pkt_cnt_l"},
> + {"ppp_promisc_tbl_hit_pkt_cnt_h"},
> + {"ppp_rsv13"},
> + {"ppp_rsv14"},
> + {"ppp_rsv15"},
> + {"ppp_rsv16"},
> +};
> +
> +static struct hns3_reg_entry dfx_rcb_reg_list[] = {
> + {"rcb_rsv0"},
> + {"rcb_fsm_dfx_st0"},
> + {"rcb_fsm_dfx_st1"},
> + {"rcb_fsm_dfx_st2"},
> + {"rcb_fifo_dfx_st0"},
> + {"rcb_fifo_dfx_st1"},
> +
> + {"rcb_fifo_dfx_st2"},
> + {"rcb_fifo_dfx_st3"},
> + {"rcb_fifo_dfx_st4"},
> + {"rcb_fifo_dfx_st5"},
> + {"rcb_fifo_dfx_st6"},
> + {"rcb_fifo_dfx_st7"},
> +
> + {"rcb_fifo_dfx_st8"},
> + {"rcb_fifo_dfx_st9"},
> + {"rcb_fifo_dfx_st10"},
> + {"rcb_fifo_dfx_st11"},
> + {"rcb_q_credit_vld_0"},
> + {"rcb_q_credit_vld_1"},
> +
> + {"rcb_q_credit_vld_2"},
> + {"rcb_q_credit_vld_3"},
> + {"rcb_q_credit_vld_4"},
> + {"rcb_q_credit_vld_5"},
> + {"rcb_q_credit_vld_6"},
> + {"rcb_q_credit_vld_7"},
> +
> + {"rcb_q_credit_vld_8"},
> + {"rcb_q_credit_vld_9"},
> + {"rcb_q_credit_vld_10"},
> + {"rcb_q_credit_vld_11"},
> + {"rcb_q_credit_vld_12"},
> + {"rcb_q_credit_vld_13"},
> +
> + {"rcb_q_credit_vld_14"},
> + {"rcb_q_credit_vld_15"},
> + {"rcb_q_credit_vld_16"},
> + {"rcb_q_credit_vld_17"},
> + {"rcb_q_credit_vld_18"},
> + {"rcb_q_credit_vld_19"},
> +
> + {"rcb_q_credit_vld_20"},
> + {"rcb_q_credit_vld_21"},
> + {"rcb_q_credit_vld_22"},
> + {"rcb_q_credit_vld_23"},
> + {"rcb_q_credit_vld_24"},
> + {"rcb_q_credit_vld_25"},
> +
> + {"rcb_q_credit_vld_26"},
> + {"rcb_q_credit_vld_27"},
> + {"rcb_q_credit_vld_28"},
> + {"rcb_q_credit_vld_29"},
> + {"rcb_q_credit_vld_30"},
> + {"rcb_q_credit_vld_31"},
> +
> + {"rcb_gro_bd_serr_cnt"},
> + {"rcb_gro_context_serr_cnt"},
> + {"rcb_rx_stash_cfg_serr_cnt"},
> + {"rcb_rcb_tx_mem_serr_cnt", "rcb_axi_rd_fbd_serr_cnt"},
> + {"rcb_gro_bd_merr_cnt"},
> + {"rcb_gro_context_merr_cnt"},
> +
> + {"rcb_rx_stash_cfg_merr_cnt"},
> + {"rcb_axi_rd_fbd_merr_cnt"},
> + {"rcb_rsv1"},
> + {"rcb_rsv2"},
> + {"rcb_rsv3"},
> + {"rcb_rsv4"},
> +};
> +
> +static struct hns3_reg_entry dfx_tqp_reg_list[] = {
> + {"dfx_tqp_q_num"},
> + {"rcb_cfg_rx_ring_tail"},
> + {"rcb_cfg_rx_ring_head"},
> + {"rcb_cfg_rx_ring_fbdnum"},
> + {"rcb_cfg_rx_ring_offset"},
> + {"rcb_cfg_rx_ring_fbdoffset"},
> +
> + {"rcb_cfg_rx_ring_pktnum_record"},
> + {"rcb_cfg_tx_ring_tail"},
> + {"rcb_cfg_tx_ring_head"},
> + {"rcb_cfg_tx_ring_fbdnum"},
> + {"rcb_cfg_tx_ring_offset"},
> + {"rcb_cfg_tx_ring_ebdnum"},
> +};
> +
> +static struct hns3_reg_entry dfx_ssu_reg_2_list[] = {
> + {"dfx_ssu2_oq_index"},
> + {"dfx_ssu2_queue_cnt"},
> + {"dfx_ssu2_rsv0"},
> + {"dfx_ssu2_rsv1"},
> + {"dfx_ssu2_rsv2"},
> + {"dfx_ssu2_rsv3"},
> +};
> +
> +struct hns3_dfx_reg_entry {
> + const struct hns3_reg_entry *regs;
> + uint32_t entry_num;
> +};
> +
> +struct hns3_dfx_reg_entry hns3_dfx_reg_list[] = {
> + {dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list)},
> + {dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list)},
> + {dfx_ssu_reg_1_list, RTE_DIM(dfx_ssu_reg_1_list)},
> + {dfx_igu_egu_reg_list, RTE_DIM(dfx_igu_egu_reg_list)},
> + {dfx_rpu_reg_0_list, RTE_DIM(dfx_rpu_reg_0_list)},
> + {dfx_rpu_reg_1_list, RTE_DIM(dfx_rpu_reg_1_list)},
> + {dfx_ncsi_reg_list, RTE_DIM(dfx_ncsi_reg_list)},
> + {dfx_rtc_reg_list, RTE_DIM(dfx_rtc_reg_list)},
> + {dfx_ppp_reg_list, RTE_DIM(dfx_ppp_reg_list)},
> + {dfx_rcb_reg_list, RTE_DIM(dfx_rcb_reg_list)},
> + {dfx_tqp_reg_list, RTE_DIM(dfx_tqp_reg_list)},
> + {dfx_ssu_reg_2_list, RTE_DIM(dfx_ssu_reg_2_list)},
> +};
> +
> static int
> hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
> uint32_t *regs_num_64_bit)
> @@ -108,6 +827,12 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
>
> *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
> *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
> + if (*regs_num_32_bit != RTE_DIM(regs_32_bit_list) ||
> + *regs_num_64_bit * HNS3_64_BIT_REG_SIZE !=
> + RTE_DIM(regs_64_bit_list)) {
> + hns3_err(hw, "Query register number differ from the list!");
> + return -EINVAL;
> + }
>
> return 0;
> }
> @@ -122,13 +847,13 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
> uint32_t len;
> int ret;
>
> - cmdq_cnt = sizeof(cmdq_reg_addrs);
> + cmdq_cnt = RTE_DIM(cmdq_reg_list);
> if (hns->is_vf)
> - common_cnt = sizeof(common_vf_reg_addrs);
> + common_cnt = sizeof(common_vf_reg_list);
> else
> - common_cnt = sizeof(common_reg_addrs);
> - ring_cnt = sizeof(ring_reg_addrs);
> - tqp_intr_cnt = sizeof(tqp_intr_reg_addrs);
> + common_cnt = RTE_DIM(common_reg_list);
> + ring_cnt = RTE_DIM(ring_reg_list);
> + tqp_intr_cnt = RTE_DIM(tqp_intr_reg_list);
>
> len = cmdq_cnt + common_cnt + ring_cnt * hw->tqps_num +
> tqp_intr_cnt * hw->intr_tqps_num;
> @@ -281,33 +1006,33 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
> size_t i;
>
> /* fetching per-PF registers values from PF PCIe register space */
> - reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
> + reg_num = RTE_DIM(cmdq_reg_list);
> for (i = 0; i < reg_num; i++)
> - *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
> + *data++ = hns3_read_dev(hw, cmdq_reg_list[i].addr);
>
> if (hns->is_vf)
> - reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
> + reg_num = RTE_DIM(common_vf_reg_list);
> else
> - reg_num = sizeof(common_reg_addrs) / sizeof(uint32_t);
> + reg_num = RTE_DIM(common_reg_list);
> for (i = 0; i < reg_num; i++)
> if (hns->is_vf)
> - *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
> + *data++ = hns3_read_dev(hw, common_vf_reg_list[i].addr);
> else
> - *data++ = hns3_read_dev(hw, common_reg_addrs[i]);
> + *data++ = hns3_read_dev(hw, common_reg_list[i].addr);
>
> - reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t);
> + reg_num = RTE_DIM(ring_reg_list);
> for (j = 0; j < hw->tqps_num; j++) {
> reg_offset = hns3_get_tqp_reg_offset(j);
> for (i = 0; i < reg_num; i++)
> *data++ = hns3_read_dev(hw,
> - ring_reg_addrs[i] + reg_offset);
> + ring_reg_list[i].addr + reg_offset);
> }
>
> - reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
> + reg_num = RTE_DIM(tqp_intr_reg_list);
> for (j = 0; j < hw->intr_tqps_num; j++) {
> reg_offset = hns3_get_tqp_intr_reg_offset(j);
> for (i = 0; i < reg_num; i++)
> - *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] +
> + *data++ = hns3_read_dev(hw, tqp_intr_reg_list[i].addr +
> reg_offset);
> }
> return data - origin_data_ptr;
next prev parent reply other threads:[~2024-03-08 9:41 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-14 1:56 [PATCH] ethdev: add dump regs for telemetry Jie Hai
2023-12-14 12:49 ` Ferruh Yigit
2024-01-09 2:19 ` Jie Hai
2024-01-09 2:41 ` Jie Hai
2024-01-09 18:06 ` Ferruh Yigit
2024-01-10 1:38 ` fengchengwen
2024-01-10 12:15 ` Ferruh Yigit
2024-01-10 14:09 ` Thomas Monjalon
2024-01-10 15:48 ` Ferruh Yigit
2024-01-11 1:55 ` fengchengwen
2024-01-11 11:11 ` Ferruh Yigit
2024-01-11 12:43 ` fengchengwen
2024-02-05 10:51 ` [PATCH v2 0/7] support dump reigser names and filter them Jie Hai
2024-02-05 10:51 ` [PATCH v2 1/7] ethdev: support report register names and filter Jie Hai
2024-02-07 17:00 ` Ferruh Yigit
2024-02-20 8:43 ` Jie Hai
2024-02-05 10:51 ` [PATCH v2 2/7] ethdev: add telemetry cmd for registers Jie Hai
2024-02-07 17:03 ` Ferruh Yigit
2024-02-22 9:01 ` Jie Hai
2024-02-05 10:51 ` [PATCH v2 3/7] net/hns3: fix dump counter of registers Jie Hai
2024-02-05 10:51 ` [PATCH v2 4/7] net/hns3: remove dump format " Jie Hai
2024-02-05 10:51 ` [PATCH v2 5/7] net/hns3: add names for registers Jie Hai
2024-02-05 10:51 ` [PATCH v2 6/7] net/hns3: support filter directly accessed registers Jie Hai
2024-02-05 10:51 ` [PATCH v2 7/7] net/hns3: support filter dump of registers Jie Hai
2024-02-20 10:58 ` [PATCH v3 0/7] support dump reigser names and filter them Jie Hai
2024-02-20 10:58 ` [PATCH v3 1/7] ethdev: support report register names and filter Jie Hai
2024-02-20 15:09 ` Stephen Hemminger
2024-02-26 2:33 ` Jie Hai
2024-02-20 15:13 ` Stephen Hemminger
2024-02-26 2:41 ` Jie Hai
2024-02-20 15:14 ` Stephen Hemminger
2024-02-26 2:57 ` Jie Hai
2024-02-20 15:14 ` Stephen Hemminger
2024-02-26 2:33 ` Jie Hai
2024-02-20 10:58 ` [PATCH v3 2/7] ethdev: add telemetry cmd for registers Jie Hai
2024-02-20 10:58 ` [PATCH v3 3/7] net/hns3: fix dump counter of registers Jie Hai
2024-02-20 10:58 ` [PATCH v3 4/7] net/hns3: remove dump format " Jie Hai
2024-02-20 10:58 ` [PATCH v3 5/7] net/hns3: add names for registers Jie Hai
2024-02-20 10:58 ` [PATCH v3 6/7] net/hns3: support filter directly accessed registers Jie Hai
2024-02-20 10:58 ` [PATCH v3 7/7] net/hns3: support filter dump of registers Jie Hai
2024-02-26 3:07 ` [PATCH v4 0/7] support dump reigser names and filter them Jie Hai
2024-02-26 3:07 ` [PATCH v4 1/7] ethdev: support report register names and filter Jie Hai
2024-02-26 8:01 ` fengchengwen
2024-03-06 7:22 ` Jie Hai
2024-02-29 9:52 ` Thomas Monjalon
2024-03-05 7:45 ` Jie Hai
2024-02-26 3:07 ` [PATCH v4 2/7] ethdev: add telemetry cmd for registers Jie Hai
2024-02-26 9:09 ` fengchengwen
2024-03-06 7:18 ` Jie Hai
2024-02-26 3:07 ` [PATCH v4 3/7] net/hns3: fix dump counter of registers Jie Hai
2024-02-26 3:07 ` [PATCH v4 4/7] net/hns3: remove dump format " Jie Hai
2024-02-26 3:07 ` [PATCH v4 5/7] net/hns3: add names for registers Jie Hai
2024-02-26 3:07 ` [PATCH v4 6/7] net/hns3: support filter directly accessed registers Jie Hai
2024-02-26 3:07 ` [PATCH v4 7/7] net/hns3: support filter dump of registers Jie Hai
2024-03-07 3:02 ` [PATCH v5 0/7] support dump reigser names and filter them Jie Hai
2024-03-07 3:02 ` [PATCH v5 1/7] ethdev: support report register names and filter Jie Hai
2024-03-08 8:09 ` lihuisong (C)
2024-03-07 3:02 ` [PATCH v5 2/7] ethdev: add telemetry cmd for registers Jie Hai
2024-03-08 8:48 ` lihuisong (C)
2024-03-07 3:02 ` [PATCH v5 3/7] net/hns3: fix dump counter of registers Jie Hai
2024-03-08 8:49 ` lihuisong (C)
2024-03-07 3:02 ` [PATCH v5 4/7] net/hns3: remove dump format " Jie Hai
2024-03-08 9:17 ` lihuisong (C)
2024-03-07 3:02 ` [PATCH v5 5/7] net/hns3: add names for registers Jie Hai
2024-03-08 9:41 ` lihuisong (C) [this message]
2024-03-08 10:24 ` lihuisong (C)
2024-03-07 3:02 ` [PATCH v5 6/7] net/hns3: support filter directly accessed registers Jie Hai
2024-03-08 9:41 ` lihuisong (C)
2024-03-07 3:02 ` [PATCH v5 7/7] net/hns3: support filter dump of registers Jie Hai
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