From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 4EA891BA0C; Wed, 25 Oct 2017 23:34:45 +0200 (CEST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2017 14:34:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,433,1503385200"; d="scan'208";a="167618489" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.241.225.45]) ([10.241.225.45]) by fmsmga006.fm.intel.com with ESMTP; 25 Oct 2017 14:34:44 -0700 To: =?UTF-8?Q?N=c3=a9lio_Laranjeiro?= , Yongseok Koh Cc: adrien.mazarguil@6wind.com, dev@dpdk.org, stable@dpdk.org, Sagi Grimberg , Alexander Solganik References: <20171022080022.13528-1-yskoh@mellanox.com> <49c39b44917c35ecaabf06f5f920d0f7e0ed0b6b.1508891141.git.yskoh@mellanox.com> <20171025091934.hvf5fv4bpkzaba2u@laranjeiro-vm> From: Ferruh Yigit Message-ID: <9fc7dd98-8add-cddd-cc57-2c17114aa410@intel.com> Date: Wed, 25 Oct 2017 14:34:43 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20171025091934.hvf5fv4bpkzaba2u@laranjeiro-vm> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v2] net/mlx5: fix Tx doorbell memory barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Oct 2017 21:34:46 -0000 On 10/25/2017 2:19 AM, Nélio Laranjeiro wrote: > On Tue, Oct 24, 2017 at 05:27:25PM -0700, Yongseok Koh wrote: >> Configuring UAR as IO-mapped makes maximum throughput decline by noticeable >> amount. If UAR is configured as write-combining register, a write memory >> barrier is needed on ringing a doorbell. rte_wmb() is mostly effective when >> the size of a burst is comparatively small. Revert the register back to >> write-combining and enforce a write memory barrier instead, except for >> vectorized Tx burst routines. Application can change it by setting >> MLX5_SHUT_UP_BF under its own necessity. >> >> Fixes: 9f9bebae5530 ("net/mlx5: don't map doorbell register to write combining") >> Cc: stable@dpdk.org >> Cc: Sagi Grimberg >> Cc: Alexander Solganik >> >> Signed-off-by: Yongseok Koh >> Acked-by: Shahaf Shuler > > Acked-by: Nelio Laranjeiro Applied to dpdk-next-net/master, thanks.