From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 783C62B84 for ; Fri, 16 Nov 2018 10:42:19 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Nov 2018 01:42:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,239,1539673200"; d="scan'208";a="89803807" Received: from pgsmsx106.gar.corp.intel.com ([10.221.44.98]) by orsmga007.jf.intel.com with ESMTP; 16 Nov 2018 01:42:17 -0800 Received: from pgsmsx101.gar.corp.intel.com ([169.254.1.244]) by PGSMSX106.gar.corp.intel.com ([169.254.9.214]) with mapi id 14.03.0415.000; Fri, 16 Nov 2018 17:42:16 +0800 From: "Zhao1, Wei" To: "Player, Timmons" CC: "dev@dpdk.org" , "Lu, Wenzhuo" , "Zhang, Qi Z" Thread-Topic: [PATCH] net/igb: fix LSC interrupt when using MSI-X Thread-Index: AQHUdsf7tZNGRyuh0k2uNoLXtooBHqVSLXBg Date: Fri, 16 Nov 2018 09:42:16 +0000 Message-ID: References: <20181107183004.21778-1-timmons.player@spirent.com> In-Reply-To: <20181107183004.21778-1-timmons.player@spirent.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [172.30.20.205] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/igb: fix LSC interrupt when using MSI-X X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Nov 2018 09:42:20 -0000 Hi, Player, Timmons > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Player, Timmons > Sent: Thursday, November 8, 2018 2:31 AM > To: Lu, Wenzhuo > Cc: dev@dpdk.org; Player, Timmons > Subject: [dpdk-dev] [PATCH] net/igb: fix LSC interrupt when using MSI-X >=20 > Take the 'other interrupt' into account when setting up MSI-X interrupts = and > use the proper mask when enabling it. Also rearm the MSI-X vector after = the > LSC interrupt fires. >=20 > This change allows both LSC and RXQ interrupts to work at the same time. >=20 > Signed-off-by: Timmons C. Player > --- > drivers/net/e1000/igb_ethdev.c | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/e1000/igb_ethdev.c > b/drivers/net/e1000/igb_ethdev.c index d9d29d22f..62c63a623 100644 > --- a/drivers/net/e1000/igb_ethdev.c > +++ b/drivers/net/e1000/igb_ethdev.c > @@ -68,6 +68,9 @@ > #define E1000_VET_VET_EXT 0xFFFF0000 > #define E1000_VET_VET_EXT_SHIFT 16 >=20 > +/* MSI-X other interrupt vector */ > +#define IGB_MSIX_OTHER_INTR_VEC 0 > + > static int eth_igb_configure(struct rte_eth_dev *dev); static int > eth_igb_start(struct rte_eth_dev *dev); static void eth_igb_stop(struct > rte_eth_dev *dev); @@ -540,6 +543,7 @@ igb_intr_enable(struct > rte_eth_dev *dev) > E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); >=20 > E1000_WRITE_REG(hw, E1000_IMS, intr->mask); > + E1000_WRITE_REG(hw, E1000_EIMS, 1 << > IGB_MSIX_OTHER_INTR_VEC); Enable of other reason interrupt is controlled by dev->data->dev_conf.intr= _conf.lsc, So why not add some "if(dev->data->dev_conf.intr_conf.lsc)" judgment statem= ent before enable it? ALL you other code has this judgement. And also, I am afraid that, this enable code to be add here is not suitabl= e, because it is related to=20 MSI-X mode interrupt, most of that is in function eth_igb_configure_msix_in= tr(), So, I suggest we can do that there with "if ()" before it. > E1000_WRITE_FLUSH(hw); > } >=20 > @@ -2768,12 +2772,15 @@ static int eth_igb_rxq_interrupt_setup(struct > rte_eth_dev *dev) > uint32_t mask, regval; > struct e1000_hw *hw =3D > E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > + int misc_shift =3D rte_intr_allow_others(intr_handle) ? 1 : 0; > struct rte_eth_dev_info dev_info; >=20 > memset(&dev_info, 0, sizeof(dev_info)); > eth_igb_infos_get(dev, &dev_info); >=20 > - mask =3D 0xFFFFFFFF >> (32 - dev_info.max_rx_queues); > + mask =3D (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << > misc_shift; > regval =3D E1000_READ_REG(hw, E1000_EIMS); > E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); >=20 > @@ -5583,13 +5590,17 @@ eth_igb_configure_msix_intr(struct rte_eth_dev > *dev) > E1000_GPIE_NSICR); > intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) > << > misc_shift; > + > + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) > + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); > + > regval =3D E1000_READ_REG(hw, E1000_EIAC); > E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); >=20 > /* enable msix_other interrupt */ > regval =3D E1000_READ_REG(hw, E1000_EIMS); > E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); > - tmpval =3D (dev->data->nb_rx_queues | E1000_IVAR_VALID) > << 8; > + tmpval =3D (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) > << 8; > E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); > } >=20 > @@ -5598,6 +5609,10 @@ eth_igb_configure_msix_intr(struct rte_eth_dev > *dev) > */ > intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << > misc_shift; > + > + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) > + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); > + > regval =3D E1000_READ_REG(hw, E1000_EIAM); > E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); >=20 > -- > 2.17.1