From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id D66C72A5E for ; Wed, 18 Oct 2017 15:00:37 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Oct 2017 06:00:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,396,1503385200"; d="scan'208";a="1026457832" Received: from irsmsx109.ger.corp.intel.com ([163.33.3.23]) by orsmga003.jf.intel.com with ESMTP; 18 Oct 2017 06:00:35 -0700 Received: from irsmsx106.ger.corp.intel.com ([169.254.8.36]) by IRSMSX109.ger.corp.intel.com ([169.254.13.28]) with mapi id 14.03.0319.002; Wed, 18 Oct 2017 14:00:34 +0100 From: "Chilikin, Andrey" To: "Zhao1, Wei" , "dev@dpdk.org" CC: "Yigit, Ferruh" , "Xing, Beilei" , "Wu, Jingjing" Thread-Topic: [dpdk-dev] [PATCH v8 1/2] net/i40e: queue region set and flush Thread-Index: AQHTQnBuT/t3zYmQZkatpGcXhFdHlKLhjstQgAdWMYCAALdwYA== Date: Wed, 18 Oct 2017 13:00:34 +0000 Message-ID: References: <1506676584-41030-1-git-send-email-wei.zhao1@intel.com> <1507712133-31875-1-git-send-email-wei.zhao1@intel.com> <1507712133-31875-2-git-send-email-wei.zhao1@intel.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTE1YzQ1YTctMTUxNS00OTVjLWExNjAtMTc4Njk0ZGU1ODRmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IngxdXlVcjJydnVqUTVBS0FDT2xEMmpKQVVaTGxvTXV1QkF2bUpHOVBxdjg9In0= x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v8 1/2] net/i40e: queue region set and flush X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Oct 2017 13:00:38 -0000 Hi Wei, Is there number of RX queues configured for the port?=20 If main_vsi->nb_used_qps reflects number of enabled RX queues, then it can = be used. Regards, Andrey > -----Original Message----- > From: Zhao1, Wei > Sent: Wednesday, October 18, 2017 4:01 AM > To: Chilikin, Andrey ; dev@dpdk.org > Cc: Yigit, Ferruh ; Xing, Beilei > ; Wu, Jingjing > Subject: RE: [dpdk-dev] [PATCH v8 1/2] net/i40e: queue region set and flu= sh >=20 > Hi=1B$B!$=1B(BAndrey >=20 > > -----Original Message----- > > From: Chilikin, Andrey > > Sent: Friday, October 13, 2017 6:07 PM > > To: Zhao1, Wei ; dev@dpdk.org > > Cc: Zhao1, Wei ; Yigit, Ferruh > > ; Xing, Beilei ; Wu, Jin= gjing > > > > Subject: RE: [dpdk-dev] [PATCH v8 1/2] net/i40e: queue region set and > flush > > > > Hi Wei > > > > Sorry for the late comment, but I was not included to the patchset CC l= ist > and > > just found this new version. > > > > > -----Original Message----- > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wei Zhao > > > Sent: Wednesday, October 11, 2017 9:56 AM > > > To: dev@dpdk.org > > > Cc: Zhao1, Wei > > > Subject: [dpdk-dev] [PATCH v8 1/2] net/i40e: queue region set and > > > flush > > > > > > > > > > > +int > > > +i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev, > > > + struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on) { > > > + int32_t ret =3D -EINVAL; > > > + struct i40e_queue_regions *info =3D &pf->queue_region; > > > + > > > + if (on) { > > > + i40e_queue_region_pf_flowtype_conf(hw, pf); > > > + > > > + ret =3D i40e_vsi_update_queue_region_mapping(hw, pf); > > > + if (ret !=3D I40E_SUCCESS) { > > > + PMD_DRV_LOG(INFO, "Failed to flush queue region > > > mapping."); > > > + return ret; > > > + } > > > + > > > + ret =3D i40e_queue_region_dcb_configure(hw, pf); > > > + if (ret !=3D I40E_SUCCESS) { > > > + PMD_DRV_LOG(INFO, "Failed to flush dcb."); > > > + return ret; > > > + } > > > + > > > + return 0; > > > + } > > > + > > > + info->queue_region_number =3D 1; > > > + info->region[0].queue_num =3D 64; > > > > Why number of queues is hardcoded to a magic number 64? How it will > work > > if VSI is enabled with smaller number of queues, for example, 1 or 6? 6= 4 is > > the maximum number of queues that can be used for RSS, but VSI might > be > > created with only few queues. >=20 > Yes, I know what is your mean, may be it should be change to >=20 > struct i40e_vsi *main_vsi =3D pf->main_vsi; > info->region[0].queue_num =3D main_vsi->nb_used_qps; >=20 > Do you think so? >=20 > > > > > + info->region[0].queue_start_index =3D 0; > > > + > > > + ret =3D i40e_vsi_update_queue_region_mapping(hw, pf); > > > + if (ret !=3D I40E_SUCCESS) > > > + PMD_DRV_LOG(INFO, "Failed to flush queue region > > > mapping."); > > > + > > > + ret =3D i40e_dcb_init_configure(dev, TRUE); > > > + if (ret !=3D I40E_SUCCESS) { > > > + PMD_DRV_LOG(INFO, "Failed to flush dcb."); > > > + pf->flags &=3D ~I40E_FLAG_DCB; > > > + } > > > + > > > + i40e_init_queue_region_conf(dev); > > > + > > > + return 0; > > > +}