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Wed, 20 Mar 2019 06:46:36 +0000 From: Shahaf Shuler To: Thomas Monjalon , Jan Viktorin , Gavin Hu , Chao Zhu CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] eal: remove redundant API description Thread-Index: AQHU3pkPi9a/vXpt70ClTUkoZHJPM6YUE//Q Date: Wed, 20 Mar 2019 06:46:36 +0000 Message-ID: References: <20190319211601.31983-1-thomas@monjalon.net> In-Reply-To: <20190319211601.31983-1-thomas@monjalon.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [193.47.165.251] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c2b804a6-5737-41c7-2707-08d6acffcc36 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR0502MB3826; x-ms-traffictypediagnostic: AM0PR0502MB3826: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shahafs@mellanox.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: c2b804a6-5737-41c7-2707-08d6acffcc36 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Mar 2019 06:46:36.0951 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB3826 Subject: Re: [dpdk-dev] [PATCH] eal: remove redundant API description X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Mar 2019 06:46:37 -0000 Tuesday, March 19, 2019 11:16 PM, Thomas Monjalon: > Subject: [dpdk-dev] [PATCH] eal: remove redundant API description >=20 > Atomic functions are described in doxygen of the file > lib/librte_eal/common/include/generic/rte_atomic.h > The copies in arch-specific files are redundant and confuse readers about= the > genericity of the API. >=20 > Signed-off-by: Thomas Monjalon Acked-by: Shahaf Shuler > --- > .../common/include/arch/arm/rte_atomic_32.h | 18 ------------------ > .../common/include/arch/ppc_64/rte_atomic.h | 18 ------------------ > .../common/include/generic/rte_atomic.h | 3 --- > 3 files changed, 39 deletions(-) >=20 > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > index 859562e59..7dc0d06d1 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > @@ -15,28 +15,10 @@ extern "C" { >=20 > #include "generic/rte_atomic.h" >=20 > -/** > - * General memory barrier. > - * > - * Guarantees that the LOAD and STORE operations generated before the > - * barrier occur before the LOAD and STORE operations generated after. > - */ > #define rte_mb() __sync_synchronize() >=20 > -/** > - * Write memory barrier. > - * > - * Guarantees that the STORE operations generated before the barrier > - * occur before the STORE operations generated after. > - */ > #define rte_wmb() do { asm volatile ("dmb st" : : : "memory"); } while > (0) >=20 > -/** > - * Read memory barrier. > - * > - * Guarantees that the LOAD operations generated before the barrier > - * occur before the LOAD operations generated after. > - */ > #define rte_rmb() __sync_synchronize() >=20 > #define rte_smp_mb() rte_mb() > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > index ce38350bd..2dd59fd78 100644 > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > @@ -49,32 +49,14 @@ extern "C" { > #include > #include "generic/rte_atomic.h" >=20 > -/** > - * General memory barrier. > - * > - * Guarantees that the LOAD and STORE operations generated before the > - * barrier occur before the LOAD and STORE operations generated after. > - */ > #define rte_mb() asm volatile("sync" : : : "memory") >=20 > -/** > - * Write memory barrier. > - * > - * Guarantees that the STORE operations generated before the barrier > - * occur before the STORE operations generated after. > - */ > #ifdef RTE_ARCH_64 > #define rte_wmb() asm volatile("lwsync" : : : "memory") > #else > #define rte_wmb() asm volatile("sync" : : : "memory") > #endif >=20 > -/** > - * Read memory barrier. > - * > - * Guarantees that the LOAD operations generated before the barrier > - * occur before the LOAD operations generated after. > - */ > #ifdef RTE_ARCH_64 > #define rte_rmb() asm volatile("lwsync" : : : "memory") > #else > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h > b/lib/librte_eal/common/include/generic/rte_atomic.h > index 4afd1acc3..e91742702 100644 > --- a/lib/librte_eal/common/include/generic/rte_atomic.h > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h > @@ -25,7 +25,6 @@ > * > * Guarantees that the LOAD and STORE operations generated before the > * barrier occur before the LOAD and STORE operations generated after. > - * This function is architecture dependent. > */ > static inline void rte_mb(void); >=20 > @@ -34,7 +33,6 @@ static inline void rte_mb(void); > * > * Guarantees that the STORE operations generated before the barrier > * occur before the STORE operations generated after. > - * This function is architecture dependent. > */ > static inline void rte_wmb(void); >=20 > @@ -43,7 +41,6 @@ static inline void rte_wmb(void); > * > * Guarantees that the LOAD operations generated before the barrier > * occur before the LOAD operations generated after. > - * This function is architecture dependent. > */ > static inline void rte_rmb(void); > ///@} > -- > 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id E718EA00E6 for ; Wed, 20 Mar 2019 07:46:39 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E0B1610A3; Wed, 20 Mar 2019 07:46:38 +0100 (CET) Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80083.outbound.protection.outlook.com [40.107.8.83]) by dpdk.org (Postfix) with ESMTP id 6C2285A for ; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR0502MB3826; H:AM0PR0502MB3795.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: vMhwj1KM2LMzUtRoBOAiQPGcNpDyUn8dcB4eozeCYJQ2VQ6hcwJJfx4yi0D8VUvSXuShLxRXf2+0TxqSBOiFvlbq30D2RqteCdSTboNNcphgOEc59OJBy2W37+SNFndn68CFOnu3N5uvlrEE1UnGowLaK9xCtlAMuEa055za/qPdGQNS7e9Dg2izsqSeTZR547VLKc9Tk4gDW1NrFi5SdCHzbuFLEpzhUepAa/hGn3CiwTxc23VYkDqeXG1Yaefm/BeNmEYLfY9ly05HLuC0P0P6738VG5PDMxVWNvvkMGZ/+MLrZKCTWvFTYHtlhQLSqr3y1RW5ayBxSHDAmnI2In9TGfF2J6QdyanIhhV8dnmIFIwh8nD19Yh1DtqoiLqkoqw9Zuwmn98ey9kNo+I+rKw8aZqUWkJPZF39aECcBLo= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: c2b804a6-5737-41c7-2707-08d6acffcc36 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Mar 2019 06:46:36.0951 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB3826 Subject: Re: [dpdk-dev] [PATCH] eal: remove redundant API description X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190320064636.4dLYmlRKjrMPBI3_1b0ZNoRP36wa-8vaueJQjNZ4X84@z> Tuesday, March 19, 2019 11:16 PM, Thomas Monjalon: > Subject: [dpdk-dev] [PATCH] eal: remove redundant API description >=20 > Atomic functions are described in doxygen of the file > lib/librte_eal/common/include/generic/rte_atomic.h > The copies in arch-specific files are redundant and confuse readers about= the > genericity of the API. >=20 > Signed-off-by: Thomas Monjalon Acked-by: Shahaf Shuler > --- > .../common/include/arch/arm/rte_atomic_32.h | 18 ------------------ > .../common/include/arch/ppc_64/rte_atomic.h | 18 ------------------ > .../common/include/generic/rte_atomic.h | 3 --- > 3 files changed, 39 deletions(-) >=20 > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > index 859562e59..7dc0d06d1 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h > @@ -15,28 +15,10 @@ extern "C" { >=20 > #include "generic/rte_atomic.h" >=20 > -/** > - * General memory barrier. > - * > - * Guarantees that the LOAD and STORE operations generated before the > - * barrier occur before the LOAD and STORE operations generated after. > - */ > #define rte_mb() __sync_synchronize() >=20 > -/** > - * Write memory barrier. > - * > - * Guarantees that the STORE operations generated before the barrier > - * occur before the STORE operations generated after. > - */ > #define rte_wmb() do { asm volatile ("dmb st" : : : "memory"); } while > (0) >=20 > -/** > - * Read memory barrier. > - * > - * Guarantees that the LOAD operations generated before the barrier > - * occur before the LOAD operations generated after. > - */ > #define rte_rmb() __sync_synchronize() >=20 > #define rte_smp_mb() rte_mb() > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > index ce38350bd..2dd59fd78 100644 > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > @@ -49,32 +49,14 @@ extern "C" { > #include > #include "generic/rte_atomic.h" >=20 > -/** > - * General memory barrier. > - * > - * Guarantees that the LOAD and STORE operations generated before the > - * barrier occur before the LOAD and STORE operations generated after. > - */ > #define rte_mb() asm volatile("sync" : : : "memory") >=20 > -/** > - * Write memory barrier. > - * > - * Guarantees that the STORE operations generated before the barrier > - * occur before the STORE operations generated after. > - */ > #ifdef RTE_ARCH_64 > #define rte_wmb() asm volatile("lwsync" : : : "memory") > #else > #define rte_wmb() asm volatile("sync" : : : "memory") > #endif >=20 > -/** > - * Read memory barrier. > - * > - * Guarantees that the LOAD operations generated before the barrier > - * occur before the LOAD operations generated after. > - */ > #ifdef RTE_ARCH_64 > #define rte_rmb() asm volatile("lwsync" : : : "memory") > #else > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h > b/lib/librte_eal/common/include/generic/rte_atomic.h > index 4afd1acc3..e91742702 100644 > --- a/lib/librte_eal/common/include/generic/rte_atomic.h > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h > @@ -25,7 +25,6 @@ > * > * Guarantees that the LOAD and STORE operations generated before the > * barrier occur before the LOAD and STORE operations generated after. > - * This function is architecture dependent. > */ > static inline void rte_mb(void); >=20 > @@ -34,7 +33,6 @@ static inline void rte_mb(void); > * > * Guarantees that the STORE operations generated before the barrier > * occur before the STORE operations generated after. > - * This function is architecture dependent. > */ > static inline void rte_wmb(void); >=20 > @@ -43,7 +41,6 @@ static inline void rte_wmb(void); > * > * Guarantees that the LOAD operations generated before the barrier > * occur before the LOAD operations generated after. > - * This function is architecture dependent. > */ > static inline void rte_rmb(void); > ///@} > -- > 2.20.1