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Sun, 3 May 2020 10:31:56 +0000 Received: from AM0PR0502MB4019.eurprd05.prod.outlook.com ([fe80::a564:a117:9022:1fee]) by AM0PR0502MB4019.eurprd05.prod.outlook.com ([fe80::a564:a117:9022:1fee%7]) with mapi id 15.20.2958.027; Sun, 3 May 2020 10:31:56 +0000 From: Matan Azrad To: Eli Britstein , "dev@dpdk.org" CC: Raslan Darawsheh , Ori Kam , Slava Ovsiienko , Eli Britstein Thread-Topic: [PATCH 2/2] net/mlx5: optimize performance for IPv4/IPv6 ethertype Thread-Index: AQHWITJZjEgMWUIqik+/3Sd29k3zM6iWJ2hg Date: Sun, 3 May 2020 10:31:56 +0000 Message-ID: References: <20200503100447.9869-1-elibr@mellanox.com> <20200503100447.9869-3-elibr@mellanox.com> In-Reply-To: <20200503100447.9869-3-elibr@mellanox.com> Accept-Language: en-US, he-IL Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mellanox.com; dkim=none (message not signed) header.d=none;mellanox.com; dmarc=none action=none header.from=mellanox.com; x-originating-ip: [77.126.88.104] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: af7ffac1-7b5d-4c3c-70b4-08d7ef4d341d x-ms-traffictypediagnostic: AM0PR0502MB3810:|AM0PR0502MB3810: x-ld-processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtFwd x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6430; 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DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: ySRT1ujxOteeH93uoFL0Vwb9S6z/nP3zwfRpyqDzqy54pRiAfkyvjc2G4rSnpPriMOy0KRASSZN6OcKkuK6RietrWPSdbAoob+w6KzOQsYPL/AD2xhVUteGrexVlmIqNXAbc9c1j9yQol3w97Svfx2sgFgcrLodGC6y4DDKBwE9sHvqxTVyxDjR33Kl2pvg1gBDjCc8aiz9o79TMIBRpnXjPdSiMMuIZQLEABzn5SztXFtlznm4CCyAa2Vc4oLFe7gIlxvvl8pfkFYccxIoPPSJ3R3rDnoinfESiIUvMyZrnpbdIfFXb1yvvPtSGpBlMCiHMzB22ilDpKfpibp7PoZbi9M7frNaSRhUUMeVKQ7tnWm6jWFmeYjVRtyv8HnSnx6C4DoV5MilFfQ2rkF+OcTLtKtjcYnERkYDmPXXhqUInEjI9ppepPQBPtcuNVqyK12gxCSBg2KyQ8/dI/Sr8MPwSQ/ivSAaskI67LJ6+fP3pDC2ZAXHjPsDEJxjNikKGOS910jYOIOP0gL00J7Kk51lIJSZsq0OX6HzjdVrJSusgJo8Qm7WEnGvw/arVXJRkX/cj6pRiX9B2eGkMK1TiWkEOXu74L3iC0+9gD/po/grSd9GnRbYD756J1BjDUOfMxNToGStjyhjdeBC6vBddMmdptpSOTnE2OilUEJgftSwdU3jGeE9So5438UgPXf/nOjMuMPTkxAY3hmLGN1eeYyW47D4doQCtHkuz+WTFfcDT89NQP/pGbbj4n5rKsObCSKjQNGCmijMMo8Am6Gpe2a6Th0vDfr2nhCTEVTYx1HA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: af7ffac1-7b5d-4c3c-70b4-08d7ef4d341d X-MS-Exchange-CrossTenant-originalarrivaltime: 03 May 2020 10:31:56.0871 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Lt184Y4F94i0o5O6zju8JxfLU2e+bkiEp7W6ZYVeXrgLlyH3E7pv45u5v/VdzTtQ4z9f2ZsDJVUW4wVhiv6cfA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB3810 Subject: Re: [dpdk-dev] [PATCH 2/2] net/mlx5: optimize performance for IPv4/IPv6 ethertype X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Eli Good optimization. Thanks. Please see comment below... From: Eli Britstein > The HW is optimized for IPv4/IPv6. For such cases avoid matching on > ethertype, and use ip_version field instead. >=20 > Signed-off-by: Eli Britstein > Acked-by: Viacheslav Ovsiienko > --- > drivers/net/mlx5/mlx5_flow_dv.c | 51 > +++++++++++++++++++++++++++++++---------- > 1 file changed, 39 insertions(+), 12 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 174d86103b..6db91ffe9e 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -5489,7 +5489,8 @@ flow_dv_set_match_ip_version(uint32_t group, > */ > static void > flow_dv_translate_item_eth(void *matcher, void *key, > - const struct rte_flow_item *item, int inner) > + const struct rte_flow_item *item, int inner, > + uint32_t group) > { > const struct rte_flow_item_eth *eth_m =3D item->mask; > const struct rte_flow_item_eth *eth_v =3D item->spec; @@ -5544,11 > +5545,22 @@ flow_dv_translate_item_eth(void *matcher, void *key, > * HW supports match on one Ethertype, the Ethertype following the > last > * VLAN tag of the packet (see PRM). > * Set match on ethertype only if ETH header is not followed by > VLAN. > + * HW is optimized for IPv4/IPv6. In such cases, avoid setting > + * ethertype, and use ip_version field instead. > */ > - MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, > - rte_be_to_cpu_16(eth_m->type)); > - l24_v =3D MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, > ethertype); > - *(uint16_t *)(l24_v) =3D eth_m->type & eth_v->type; > + if (eth_v->type =3D=3D RTE_BE16(RTE_ETHER_TYPE_IPV4) && > + eth_m->type =3D=3D 0xFFFF) { The check here is only for exact match in ethertype field (in vlan header t= oo). But for the next flows with empty mask on ethertype: Eth / ipv4 Eth / vlan/ ipv4 The optimization is not on. Maybe need to zero the match on ethertype in IPV4 translate? Same for IPV6 below... > + flow_dv_set_match_ip_version(group, headers_v, > headers_m, 4); > + } else if (eth_v->type =3D=3D RTE_BE16(RTE_ETHER_TYPE_IPV6) && > + eth_m->type =3D=3D 0xFFFF) { > + flow_dv_set_match_ip_version(group, headers_v, > headers_m, 6); > + } else { > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, > + rte_be_to_cpu_16(eth_m->type)); > + l24_v =3D MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, > + ethertype); > + *(uint16_t *)(l24_v) =3D eth_m->type & eth_v->type; > + } > } >=20 > /** > @@ -5569,7 +5581,7 @@ static void > flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow, > void *matcher, void *key, > const struct rte_flow_item *item, > - int inner) > + int inner, uint32_t group) > { > const struct rte_flow_item_vlan *vlan_m =3D item->mask; > const struct rte_flow_item_vlan *vlan_v =3D item->spec; @@ -5607,10 > +5619,23 @@ flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow, > MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12); > MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> > 13); > MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> > 13); > - MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, > - rte_be_to_cpu_16(vlan_m->inner_type)); > - MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, > - rte_be_to_cpu_16(vlan_m->inner_type & vlan_v- > >inner_type)); > + /* > + * HW is optimized for IPv4/IPv6. In such cases, avoid setting > + * ethertype, and use ip_version field instead. > + */ > + if (vlan_v->inner_type =3D=3D RTE_BE16(RTE_ETHER_TYPE_IPV4) && > + vlan_m->inner_type =3D=3D 0xFFFF) { > + flow_dv_set_match_ip_version(group, headers_v, > headers_m, 4); > + } else if (vlan_v->inner_type =3D=3D RTE_BE16(RTE_ETHER_TYPE_IPV6) > && > + vlan_m->inner_type =3D=3D 0xFFFF) { > + flow_dv_set_match_ip_version(group, headers_v, > headers_m, 6); > + } else { > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, > + rte_be_to_cpu_16(vlan_m->inner_type)); > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, > + rte_be_to_cpu_16(vlan_m->inner_type & > + vlan_v->inner_type)); > + } > } >=20 > /** > @@ -7944,7 +7969,8 @@ __flow_dv_translate(struct rte_eth_dev *dev, > break; > case RTE_FLOW_ITEM_TYPE_ETH: > flow_dv_translate_item_eth(match_mask, > match_value, > - items, tunnel); > + items, tunnel, > + dev_flow->dv.group); > matcher.priority =3D MLX5_PRIORITY_MAP_L2; > last_item =3D tunnel ? MLX5_FLOW_LAYER_INNER_L2 : > MLX5_FLOW_LAYER_OUTER_L2; > @@ -7952,7 +7978,8 @@ __flow_dv_translate(struct rte_eth_dev *dev, > case RTE_FLOW_ITEM_TYPE_VLAN: > flow_dv_translate_item_vlan(dev_flow, > match_mask, match_value, > - items, tunnel); > + items, tunnel, > + dev_flow->dv.group); > matcher.priority =3D MLX5_PRIORITY_MAP_L2; > last_item =3D tunnel ? (MLX5_FLOW_LAYER_INNER_L2 > | >=20 > MLX5_FLOW_LAYER_INNER_VLAN) : > -- > 2.14.5