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* [dpdk-dev] [PATCH] net/mlx5: fix indexed pool bitmap initialization
@ 2020-04-28  9:13 Suanming Mou
  2020-04-29  1:47 ` Ruifeng Wang
  2020-04-30 10:29 ` Raslan Darawsheh
  0 siblings, 2 replies; 3+ messages in thread
From: Suanming Mou @ 2020-04-28  9:13 UTC (permalink / raw)
  To: Matan Azrad, Shahaf Shuler, Viacheslav Ovsiienko
  Cc: dev, rasland, Lijian.Zhang

Currently, the indexed memory pool bitmap start address is not aligned
to cacheline size explicitly. The bitmap initialization requires the
address should be cacheline aligned. In that case, the initialization
maybe failed if the address is not cacheline aligned.

Add RTE_CACHE_LINE_ROUNDUP() to the trunk size calculation to make sure
the bitmap offset address will start with cacheline aligned.

Fixes: a3cf59f56c47 ("net/mlx5: add indexed memory pool")

Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Tested-by: Lijian Zhang <Lijian.Zhang@arm.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
 drivers/net/mlx5/mlx5_utils.c | 10 +++++++---
 drivers/net/mlx5/mlx5_utils.h |  2 +-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c
index 2146ffd..d29fbcb 100644
--- a/drivers/net/mlx5/mlx5_utils.c
+++ b/drivers/net/mlx5/mlx5_utils.c
@@ -265,7 +265,9 @@ struct mlx5_indexed_pool *
 	trunk_size += sizeof(*trunk);
 	data_size = mlx5_trunk_size_get(pool, idx);
 	bmp_size = rte_bitmap_get_memory_footprint(data_size);
-	trunk_size += data_size * pool->cfg.size + bmp_size;
+	/* rte_bitmap requires memory cacheline aligned. */
+	trunk_size += RTE_CACHE_LINE_ROUNDUP(data_size * pool->cfg.size);
+	trunk_size += bmp_size;
 	trunk = pool->cfg.malloc(pool->cfg.type, trunk_size,
 				 RTE_CACHE_LINE_SIZE, rte_socket_id());
 	if (!trunk)
@@ -278,8 +280,10 @@ struct mlx5_indexed_pool *
 	MLX5_ASSERT(pool->free_list == TRUNK_INVALID);
 	pool->free_list = idx;
 	/* Mark all entries as available. */
-	trunk->bmp = rte_bitmap_init_with_all_set(data_size,
-		     &trunk->data[data_size * pool->cfg.size], bmp_size);
+	trunk->bmp = rte_bitmap_init_with_all_set(data_size, &trunk->data
+		     [RTE_CACHE_LINE_ROUNDUP(data_size * pool->cfg.size)],
+		     bmp_size);
+	MLX5_ASSERT(trunk->bmp);
 	pool->n_trunk_valid++;
 #ifdef POOL_DEBUG
 	pool->trunk_new++;
diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h
index d81ace3..1248caa 100644
--- a/drivers/net/mlx5/mlx5_utils.h
+++ b/drivers/net/mlx5/mlx5_utils.h
@@ -115,7 +115,7 @@ struct mlx5_indexed_trunk {
 	uint32_t next; /* Next free trunk in free list. */
 	uint32_t free; /* Free entries available */
 	struct rte_bitmap *bmp;
-	uint8_t data[] __rte_cache_min_aligned; /* Entry data start. */
+	uint8_t data[] __rte_cache_aligned; /* Entry data start. */
 };
 
 struct mlx5_indexed_pool {
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [dpdk-dev] [PATCH] net/mlx5: fix indexed pool bitmap initialization
  2020-04-28  9:13 [dpdk-dev] [PATCH] net/mlx5: fix indexed pool bitmap initialization Suanming Mou
@ 2020-04-29  1:47 ` Ruifeng Wang
  2020-04-30 10:29 ` Raslan Darawsheh
  1 sibling, 0 replies; 3+ messages in thread
From: Ruifeng Wang @ 2020-04-29  1:47 UTC (permalink / raw)
  To: Suanming Mou, Matan Azrad, Shahaf Shuler, Viacheslav Ovsiienko
  Cc: dev, rasland, Lijian Zhang


> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Suanming Mou
> Sent: Tuesday, April 28, 2020 5:14 PM
> To: Matan Azrad <matan@mellanox.com>; Shahaf Shuler
> <shahafs@mellanox.com>; Viacheslav Ovsiienko
> <viacheslavo@mellanox.com>
> Cc: dev@dpdk.org; rasland@mellanox.com; Lijian Zhang
> <Lijian.Zhang@arm.com>
> Subject: [dpdk-dev] [PATCH] net/mlx5: fix indexed pool bitmap initialization
>
> Currently, the indexed memory pool bitmap start address is not aligned to
> cacheline size explicitly. The bitmap initialization requires the address should
> be cacheline aligned. In that case, the initialization maybe failed if the
> address is not cacheline aligned.
>
> Add RTE_CACHE_LINE_ROUNDUP() to the trunk size calculation to make sure
> the bitmap offset address will start with cacheline aligned.
>
> Fixes: a3cf59f56c47 ("net/mlx5: add indexed memory pool")
>
> Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
> Tested-by: Lijian Zhang <Lijian.Zhang@arm.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> ---
>  drivers/net/mlx5/mlx5_utils.c | 10 +++++++---
> drivers/net/mlx5/mlx5_utils.h |  2 +-
>  2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c
> index 2146ffd..d29fbcb 100644
> --- a/drivers/net/mlx5/mlx5_utils.c
> +++ b/drivers/net/mlx5/mlx5_utils.c
> @@ -265,7 +265,9 @@ struct mlx5_indexed_pool *
>  trunk_size += sizeof(*trunk);
>  data_size = mlx5_trunk_size_get(pool, idx);
>  bmp_size = rte_bitmap_get_memory_footprint(data_size);
> -trunk_size += data_size * pool->cfg.size + bmp_size;
> +/* rte_bitmap requires memory cacheline aligned. */
> +trunk_size += RTE_CACHE_LINE_ROUNDUP(data_size * pool-
> >cfg.size);
> +trunk_size += bmp_size;
>  trunk = pool->cfg.malloc(pool->cfg.type, trunk_size,
>   RTE_CACHE_LINE_SIZE, rte_socket_id());
>  if (!trunk)
> @@ -278,8 +280,10 @@ struct mlx5_indexed_pool *
>  MLX5_ASSERT(pool->free_list == TRUNK_INVALID);
>  pool->free_list = idx;
>  /* Mark all entries as available. */
> -trunk->bmp = rte_bitmap_init_with_all_set(data_size,
> -     &trunk->data[data_size * pool->cfg.size], bmp_size);
> +trunk->bmp = rte_bitmap_init_with_all_set(data_size, &trunk->data
> +     [RTE_CACHE_LINE_ROUNDUP(data_size * pool->cfg.size)],
> +     bmp_size);
> +MLX5_ASSERT(trunk->bmp);
>  pool->n_trunk_valid++;
>  #ifdef POOL_DEBUG
>  pool->trunk_new++;
> diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h
> index d81ace3..1248caa 100644
> --- a/drivers/net/mlx5/mlx5_utils.h
> +++ b/drivers/net/mlx5/mlx5_utils.h
> @@ -115,7 +115,7 @@ struct mlx5_indexed_trunk {
>  uint32_t next; /* Next free trunk in free list. */
>  uint32_t free; /* Free entries available */
>  struct rte_bitmap *bmp;
> -uint8_t data[] __rte_cache_min_aligned; /* Entry data start. */
> +uint8_t data[] __rte_cache_aligned; /* Entry data start. */
>  };
>
>  struct mlx5_indexed_pool {
> --
> 1.8.3.1
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>

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^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [dpdk-dev] [PATCH] net/mlx5: fix indexed pool bitmap initialization
  2020-04-28  9:13 [dpdk-dev] [PATCH] net/mlx5: fix indexed pool bitmap initialization Suanming Mou
  2020-04-29  1:47 ` Ruifeng Wang
@ 2020-04-30 10:29 ` Raslan Darawsheh
  1 sibling, 0 replies; 3+ messages in thread
From: Raslan Darawsheh @ 2020-04-30 10:29 UTC (permalink / raw)
  To: Suanming Mou, Matan Azrad, Shahaf Shuler, Slava Ovsiienko
  Cc: dev, Lijian.Zhang

Hi,

> -----Original Message-----
> From: Suanming Mou <suanmingm@mellanox.com>
> Sent: Tuesday, April 28, 2020 12:14 PM
> To: Matan Azrad <matan@mellanox.com>; Shahaf Shuler
> <shahafs@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>
> Cc: dev@dpdk.org; Raslan Darawsheh <rasland@mellanox.com>;
> Lijian.Zhang@arm.com
> Subject: [PATCH] net/mlx5: fix indexed pool bitmap initialization
> 
> Currently, the indexed memory pool bitmap start address is not aligned
> to cacheline size explicitly. The bitmap initialization requires the
> address should be cacheline aligned. In that case, the initialization
> maybe failed if the address is not cacheline aligned.
> 
> Add RTE_CACHE_LINE_ROUNDUP() to the trunk size calculation to make sure
> the bitmap offset address will start with cacheline aligned.
> 
> Fixes: a3cf59f56c47 ("net/mlx5: add indexed memory pool")
> 
> Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
> Tested-by: Lijian Zhang <Lijian.Zhang@arm.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> ---
>  drivers/net/mlx5/mlx5_utils.c | 10 +++++++---
>  drivers/net/mlx5/mlx5_utils.h |  2 +-
>  2 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c
> index 2146ffd..d29fbcb 100644
> --- a/drivers/net/mlx5/mlx5_utils.c
> +++ b/drivers/net/mlx5/mlx5_utils.c
> @@ -265,7 +265,9 @@ struct mlx5_indexed_pool *
>  	trunk_size += sizeof(*trunk);
>  	data_size = mlx5_trunk_size_get(pool, idx);
>  	bmp_size = rte_bitmap_get_memory_footprint(data_size);
> -	trunk_size += data_size * pool->cfg.size + bmp_size;
> +	/* rte_bitmap requires memory cacheline aligned. */
> +	trunk_size += RTE_CACHE_LINE_ROUNDUP(data_size * pool-
> >cfg.size);
> +	trunk_size += bmp_size;
>  	trunk = pool->cfg.malloc(pool->cfg.type, trunk_size,
>  				 RTE_CACHE_LINE_SIZE, rte_socket_id());
>  	if (!trunk)
> @@ -278,8 +280,10 @@ struct mlx5_indexed_pool *
>  	MLX5_ASSERT(pool->free_list == TRUNK_INVALID);
>  	pool->free_list = idx;
>  	/* Mark all entries as available. */
> -	trunk->bmp = rte_bitmap_init_with_all_set(data_size,
> -		     &trunk->data[data_size * pool->cfg.size], bmp_size);
> +	trunk->bmp = rte_bitmap_init_with_all_set(data_size, &trunk->data
> +		     [RTE_CACHE_LINE_ROUNDUP(data_size * pool-
> >cfg.size)],
> +		     bmp_size);
> +	MLX5_ASSERT(trunk->bmp);
>  	pool->n_trunk_valid++;
>  #ifdef POOL_DEBUG
>  	pool->trunk_new++;
> diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h
> index d81ace3..1248caa 100644
> --- a/drivers/net/mlx5/mlx5_utils.h
> +++ b/drivers/net/mlx5/mlx5_utils.h
> @@ -115,7 +115,7 @@ struct mlx5_indexed_trunk {
>  	uint32_t next; /* Next free trunk in free list. */
>  	uint32_t free; /* Free entries available */
>  	struct rte_bitmap *bmp;
> -	uint8_t data[] __rte_cache_min_aligned; /* Entry data start. */
> +	uint8_t data[] __rte_cache_aligned; /* Entry data start. */
>  };
> 
>  struct mlx5_indexed_pool {
> --
> 1.8.3.1


Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2020-04-30 10:30 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2020-04-28  9:13 [dpdk-dev] [PATCH] net/mlx5: fix indexed pool bitmap initialization Suanming Mou
2020-04-29  1:47 ` Ruifeng Wang
2020-04-30 10:29 ` Raslan Darawsheh

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