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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0802MB2164 Subject: Re: [dpdk-dev] [PATCH v7 02/17] lib/ring: apis to support configurable element size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > > > > > + > > > > > > > +static __rte_always_inline void enqueue_elems_128(struct > > > > > > > +rte_ring *r, uint32_t prod_head, const void *obj_table, > > > > > > > +uint32_t n) { unsigned int i; const uint32_t size =3D > > > > > > > +r->size; uint32_t idx =3D prod_head & r->mask; __uint128_t > > > > > > > +*ring =3D (__uint128_t *)&r[1]; const __uint128_t *obj =3D > > > > > > > +(const __uint128_t *)obj_table; if (likely(idx + n < size)) > > > > > > > +{ for (i =3D 0; i < (n & ~0x1); i +=3D 2, idx +=3D 2) { ring= [idx] > > > > > > > +=3D obj[i]; ring[idx + 1] =3D obj[i + 1]; > > > > > > > > > > > > > > > > > > AFAIK, that implies 16B aligned obj_table... > > > > > > Would it always be the case? > > > > > I am not sure from the compiler perspective. > > > > > At least on Arm architecture, unaligned access (address that is > > > > > accessed is not aligned to the size of the data element being > > > > > accessed) will result in faults or require additional cycles. > > > > > So, aligning on > > > 16B should be fine. > > > > Further, I would be changing this to use 'rte_int128_t' as > > > > '__uint128_t' is > > > not defined on 32b systems. > > > > > > What I am trying to say: with this code we imply new requirement for > > > elems > > The only existing use case in DPDK for 16B is the event ring. The event= ring > already does similar kind of copy (using 'struct rte_event'). > > So, there is no change in expectations for event ring. > > For future code, I think this expectation should be fine since it allow= s for > optimal code. > > > > > in the ring: when sizeof(elem)=3D=3D16 it's alignment also has to be = at least > 16. > > > Which from my perspective is not ideal. > > Any reasoning? >=20 > New implicit requirement and inconsistency. > Code like that: >=20 > struct ring_elem {uint64_t a, b;}; > .... > struct ring_elem elem; > rte_ring_dequeue_elem(ring, &elem, sizeof(elem)); >=20 > might cause a crash. The alignment here is 8B. Assuming that instructions generated will require= 16B alignment, it will result in a crash, if configured to generate except= ion. But, these instructions are not atomic instructions. At least on aarch64, u= naligned access will not result in an exception for non-atomic loads/stores= . I believe it is the same behavior for x86 as well. > While exactly the same code with: >=20 > struct ring_elem {uint64_t a, b, c;}; OR struct ring_elem {uint64_t a, b,= c, d;}; >=20 > will work ok. The alignment for these structures is still 8B. Are you saying this will wo= rk because these will be copied using pointer to uint32_t (whose alignment = is 4B)? >=20 > > > > > Note that for elem sizes > 16 (24, 32), there is no such constraint. > > The rest of them need to be aligned on 4B boundary. However, this shoul= d > not affect the existing code. > > The code for 8B and 16B is kept as is to ensure the performance is not > affected for the existing code.