From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4735DA3201 for ; Mon, 21 Oct 2019 09:21:22 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6098D2BAC; Mon, 21 Oct 2019 09:21:20 +0200 (CEST) Received: from EUR03-AM5-obe.outbound.protection.outlook.com (mail-eopbgr30082.outbound.protection.outlook.com [40.107.3.82]) by dpdk.org (Postfix) with ESMTP id 29EC92B9D for ; Mon, 21 Oct 2019 09:21:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NuPoB5t9othvSlmctt94SXIgfE6zmN6hoT9cJhvrbZo=; b=kW++LS9JFiPNDAz5xPrejEw1Emnmc0Y309lbV0Xb1UirwsJCNJ0ALfsbLZ/XJye/uml+dCuA4uO3bpbeXru0GVVTwV3wubgSlmfprOct5K6ihAmtBzN9x0OJsksagv9dR/qGyPYYVcoZ4NwSokIGSd9UDjuaQBaD0ze+e3VAiG4= Received: from VI1PR08CA0186.eurprd08.prod.outlook.com (2603:10a6:800:d2::16) by VI1PR08MB3023.eurprd08.prod.outlook.com (2603:10a6:803:4e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.22; Mon, 21 Oct 2019 07:21:15 +0000 Received: from AM5EUR03FT039.eop-EUR03.prod.protection.outlook.com (2a01:111:f400:7e08::209) by VI1PR08CA0186.outlook.office365.com (2603:10a6:800:d2::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2367.21 via Frontend Transport; Mon, 21 Oct 2019 07:21:15 +0000 Authentication-Results: spf=temperror (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dpdk.org; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dpdk.org; dmarc=none action=none header.from=arm.com; Received-SPF: TempError (protection.outlook.com: error in processing during lookup of arm.com: DNS Timeout) Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM5EUR03FT039.mail.protection.outlook.com (10.152.17.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2305.15 via Frontend Transport; Mon, 21 Oct 2019 07:21:14 +0000 Received: ("Tessian outbound 0939a6bab6b1:v33"); Mon, 21 Oct 2019 07:21:13 +0000 X-CR-MTA-TID: 64aa7808 Received: from 1a2de5b08d8e.1 (ip-172-16-0-2.eu-west-1.compute.internal [104.47.8.58]) by 64aa7808-outbound-1.mta.getcheckrecipient.com id E004AF65-5E20-4C2B-B2CA-9F4900D4733A.1; Mon, 21 Oct 2019 07:21:08 +0000 Received: from EUR03-AM5-obe.outbound.protection.outlook.com (mail-am5eur03lp2058.outbound.protection.outlook.com [104.47.8.58]) by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 1a2de5b08d8e.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Mon, 21 Oct 2019 07:21:08 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=moMwyFbHoEBYQwHZb5UqHmVLBtws0WfDPvWxLq2bKZi54Gqy6gw+jVdJ82aonifGvyrvnbF8TMeTS3pqV9y8dmpJEpTtalIF3VTfM//boxBrzYmPYYEi+lxrBX1lSc7DKluzSyWq2C8kfyoA71fFNeey7UzsDXXUbF9qMYOUPlm/MX10/QBYxhS/9Cscb8XGyBXmFvdzUfq9+g19PVvDFYDMOV0XOvsO6KUTBjEL3hWJZPf1DqqAgElkov28drIpSR7ItpnBZMf5+GzfHdkJJC8qZTtLRIJTidc3RtunVY3WzDX1YqhVZZzkLXysNawOXfGRJXKz96E+V6n3EmgUCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NuPoB5t9othvSlmctt94SXIgfE6zmN6hoT9cJhvrbZo=; b=mqmepmWUNhma+dZW1jDaj0UYrP74KIjFNwqsgHa+cWuLu3oYZA9sSvF49/bhgb37BUsV8W1+Q/tghvwpmMLsKXd88gKFhZCF7lRE+yWRKH82dAW6V+pCC9TbQ33oM9O22uvcUk537i+tFMQvzzM0ZTT6MEWWkYOtERiTNR1qmUPK7uGvAtr7vXB88QcLonGfBdRvFyvhq+r9VyFpdQ4XLLMK5WrMTdluFr7AgZRQudZ/jW0hg+LWIkp1uSwSoKf7nG97DFYbNVAEu1zqeb7TiTDsLJUSXo0H3zNlXJwRbRXA7185tPyTVtLZVwE6fIZgVw8sOsFykwdkSWEmQZ9P9A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NuPoB5t9othvSlmctt94SXIgfE6zmN6hoT9cJhvrbZo=; b=kW++LS9JFiPNDAz5xPrejEw1Emnmc0Y309lbV0Xb1UirwsJCNJ0ALfsbLZ/XJye/uml+dCuA4uO3bpbeXru0GVVTwV3wubgSlmfprOct5K6ihAmtBzN9x0OJsksagv9dR/qGyPYYVcoZ4NwSokIGSd9UDjuaQBaD0ze+e3VAiG4= Received: from AM0PR08MB5363.eurprd08.prod.outlook.com (52.132.214.213) by AM0PR08MB2964.eurprd08.prod.outlook.com (52.134.93.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2367.21; Mon, 21 Oct 2019 07:21:06 +0000 Received: from AM0PR08MB5363.eurprd08.prod.outlook.com ([fe80::b483:301f:e382:a94d]) by AM0PR08MB5363.eurprd08.prod.outlook.com ([fe80::b483:301f:e382:a94d%6]) with mapi id 15.20.2347.029; Mon, 21 Oct 2019 07:21:06 +0000 From: "Gavin Hu (Arm Technology China)" To: "Ananyev, Konstantin" , "dev@dpdk.org" CC: nd , "thomas@monjalon.net" , "stephen@networkplumber.org" , "hemant.agrawal@nxp.com" , "jerinj@marvell.com" , "pbhagavatula@marvell.com" , Honnappa Nagarahalli , "Ruifeng Wang (Arm Technology China)" , "Phil Yang (Arm Technology China)" , Steve Capper , nd Thread-Topic: [dpdk-dev] [PATCH v7 2/7] eal: add the APIs to wait until equal Thread-Index: AQHVdPZmZDiMClkJakOV0igd5gNYTKde79SAgAXmCcA= Date: Mon, 21 Oct 2019 07:21:06 +0000 Message-ID: References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> <1569562904-43950-3-git-send-email-gavin.hu@arm.com> <2601191342CEEE43887BDE71AB97725801A8C6A834@IRSMSX104.ger.corp.intel.com> In-Reply-To: <2601191342CEEE43887BDE71AB97725801A8C6A834@IRSMSX104.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 17015b56-4d74-42a3-87f4-2924b1655905.0 x-checkrecipientchecked: true Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Gavin.Hu@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email X-MS-Office365-Filtering-Correlation-Id: aee253f8-de22-48ae-ced3-08d755f74211 X-MS-Office365-Filtering-HT: Tenant X-MS-TrafficTypeDiagnostic: AM0PR08MB2964:|AM0PR08MB2964:|VI1PR08MB3023: x-ld-processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:10000;OLM:10000; x-forefront-prvs: 0197AFBD92 X-Forefront-Antispam-Report-Untrusted: SFV:NSPM; SFS:(10009020)(4636009)(39860400002)(136003)(346002)(366004)(396003)(376002)(13464003)(189003)(199004)(8936002)(66946007)(76116006)(9686003)(26005)(3846002)(6116002)(55016002)(6246003)(74316002)(99286004)(229853002)(2906002)(14444005)(66066001)(478600001)(256004)(71200400001)(71190400001)(52536014)(33656002)(6436002)(66446008)(66476007)(64756008)(66556008)(4326008)(86362001)(11346002)(316002)(7736002)(25786009)(55236004)(110136005)(2501003)(476003)(305945005)(14454004)(7696005)(8676002)(6506007)(53546011)(76176011)(446003)(5660300002)(54906003)(486006)(186003)(81156014)(81166006)(102836004)(21314003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR08MB2964; H:AM0PR08MB5363.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 3QbzrPauXclyVO/dQovIzxGX4s0sK98zhZrm0EhQ0q46trm0nw+dKm6nQK+GPsPItWq1ZYAJfoQAkvPaGw9f/hJxBsbkzSTAjNq8i/bu5nBELDeM3OWYPiKTI/yqhCDl073ZRF1EuFFCHoU9NNMwEISFgKPilDt4FAiotm/YKwPLexOc3mg4NazUccjBMFLa3EdYaEsuZBt6OY3DXXnqcWM+3x3Ih9hLb8kj1J8wlMLi2XChUugqxjq8gvpicLvxQFfoAgXYLRFhAOVk1KAlzt4AZlZRonnRbvZ9fh18ukUWJNmDU0ceIukIhzjOTcVuhi60AlXh/q/OZWV5N9/KFpIaadFOH65wIU48N78KiCvPUgs1T+q9IrMYAobMd1kLMdyqI0d6eIgMh/KF6/wvzSoOUEOvfGyJDdg1coANl2EWtdnCbhlSTU98OzFlu2mc Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB2964 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Gavin.Hu@arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT039.eop-EUR03.prod.protection.outlook.com X-Forefront-Antispam-Report: CIP:63.35.35.123; IPV:CAL; SCL:-1; CTRY:IE; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(39850400004)(346002)(396003)(136003)(376002)(13464003)(189003)(199004)(3846002)(446003)(63350400001)(76176011)(52536014)(23726003)(6116002)(99286004)(47776003)(486006)(70586007)(6246003)(356004)(66066001)(126002)(70206006)(476003)(11346002)(26005)(7696005)(97756001)(2501003)(336012)(102836004)(186003)(55016002)(6506007)(53546011)(86362001)(5660300002)(9686003)(316002)(36906005)(14444005)(4326008)(7736002)(305945005)(74316002)(14454004)(229853002)(8936002)(8746002)(22756006)(81156014)(25786009)(54906003)(8676002)(110136005)(81166006)(2906002)(33656002)(50466002)(76130400001)(26826003)(478600001)(46406003)(21314003); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR08MB3023; H:64aa7808-outbound-1.mta.getcheckrecipient.com; FPR:; SPF:TempError; LANG:en; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; MX:1; A:1; X-MS-Office365-Filtering-Correlation-Id-Prvs: f0f91b41-811e-43fb-765d-08d755f73d2a NoDisclaimer: True X-Forefront-PRVS: 0197AFBD92 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BO3q0MHvMewz9auHwwSID38hHeZn9HijBNJVUFH4eBpNTtbXcTX9d3yl13s7QrzVYJ121qUggRTbmVemxAf/cGR4KN8i/tvuSv6pA4CfCt1rH78dRf4ijco71iN0AovtJwB+7V5gbSbZMZUAa8c1gPa6cNC7xLp+umpZhhMxLHknGxRqvMjlY0WIWn96Dyt0jH2o/SWXGo0zw8VkfUCRRM8O90QWHu/0Rk1QzCfurmpS/JinwJE5Yl16rqe4TOH3e21PkWsTP8IrEeZrgaiPXwEParz6A7/g+G4nC+0jfxvf8Pzg1aF+WDLVHtQIlmJhs25LbcpCTD8B6ngm6FT2uCFFfFcmxlQUg0o3XkiB4GKZvbNqfrFR73AdXTGJwjbvHYh3yj3p8JgfIHRfykyn2lU2BxQ/Blk7z43TgZs7MZ45/Kpu1A8/58rowc+GxsKz X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2019 07:21:14.9380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aee253f8-de22-48ae-ced3-08d755f74211 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3023 Subject: Re: [dpdk-dev] [PATCH v7 2/7] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Ananyev, Konstantin > Sent: Thursday, October 17, 2019 9:15 PM > To: Gavin Hu (Arm Technology China) ; dev@dpdk.org > Cc: nd ; thomas@monjalon.net; > stephen@networkplumber.org; hemant.agrawal@nxp.com; > jerinj@marvell.com; pbhagavatula@marvell.com; Honnappa Nagarahalli > ; Ruifeng Wang (Arm Technology China) > ; Phil Yang (Arm Technology China) > ; Steve Capper > Subject: RE: [dpdk-dev] [PATCH v7 2/7] eal: add the APIs to wait until eq= ual >=20 > Hi Gavin, >=20 > > > > The rte_wait_until_equal_xx APIs abstract the functionality of > > 'polling for a memory location to become equal to a given value'. > > > > Add the RTE_ARM_USE_WFE configuration entry for aarch64, disabled > > by default. When it is enabled, the above APIs will call WFE instructio= n > > to save CPU cycles and power. > > > > Signed-off-by: Gavin Hu > > Reviewed-by: Ruifeng Wang > > Reviewed-by: Steve Capper > > Reviewed-by: Ola Liljedahl > > Reviewed-by: Honnappa Nagarahalli > > Reviewed-by: Phil Yang > > Acked-by: Pavan Nikhilesh > > --- > > config/arm/meson.build | 1 + > > config/common_base | 5 + > > .../common/include/arch/arm/rte_pause_64.h | 30 ++++++ > > lib/librte_eal/common/include/generic/rte_pause.h | 106 > +++++++++++++++++++++ > > 4 files changed, 142 insertions(+) > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build > > index 979018e..b4b4cac 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -26,6 +26,7 @@ flags_common_default =3D [ > > ['RTE_LIBRTE_AVP_PMD', false], > > > > ['RTE_SCHED_VECTOR', false], > > + ['RTE_ARM_USE_WFE', false], > > ] > > > > flags_generic =3D [ > > diff --git a/config/common_base b/config/common_base > > index 8ef75c2..8861713 100644 > > --- a/config/common_base > > +++ b/config/common_base > > @@ -111,6 +111,11 @@ CONFIG_RTE_MAX_VFIO_CONTAINERS=3D64 > > CONFIG_RTE_MALLOC_DEBUG=3Dn > > CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > > CONFIG_RTE_USE_LIBBSD=3Dn > > +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs, > > +# calling these APIs put the cores in low power state while waiting > > +# for the memory address to become equal to the expected value. > > +# This is supported only by aarch64. > > +CONFIG_RTE_ARM_USE_WFE=3Dn > > > > # > > # Recognize/ignore the AVX/AVX512 CPU flags for performance/power > testing. > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > index 93895d3..dabde17 100644 > > --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > @@ -1,5 +1,6 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > * Copyright(c) 2017 Cavium, Inc > > + * Copyright(c) 2019 Arm Limited > > */ > > > > #ifndef _RTE_PAUSE_ARM64_H_ > > @@ -17,6 +18,35 @@ static inline void rte_pause(void) > > asm volatile("yield" ::: "memory"); > > } > > > > +#ifdef RTE_ARM_USE_WFE > > +#define __WAIT_UNTIL_EQUAL(name, asm_op, wide, type) \ > > +static __rte_always_inline void \ > > +rte_wait_until_equal_##name(volatile type * addr, type expected) \ > > +{ \ > > + type tmp; \ > > + asm volatile( \ > > + #asm_op " %" #wide "[tmp], %[addr]\n" \ > > + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \ > > + "b.eq 2f\n" \ > > + "sevl\n" \ > > + "1: wfe\n" \ > > + #asm_op " %" #wide "[tmp], %[addr]\n" \ > > + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \ > > + "bne 1b\n" \ > > + "2:\n" \ > > + : [tmp] "=3D&r" (tmp) \ > > + : [addr] "Q"(*addr), [expected] "r"(expected) \ > > + : "cc", "memory"); \ > > +} > > +/* Wait for *addr to be updated with expected value */ > > +__WAIT_UNTIL_EQUAL(relaxed_16, ldxrh, w, uint16_t) > > +__WAIT_UNTIL_EQUAL(acquire_16, ldaxrh, w, uint16_t) > > +__WAIT_UNTIL_EQUAL(relaxed_32, ldxr, w, uint32_t) > > +__WAIT_UNTIL_EQUAL(acquire_32, ldaxr, w, uint32_t) > > +__WAIT_UNTIL_EQUAL(relaxed_64, ldxr, x, uint64_t) > > +__WAIT_UNTIL_EQUAL(acquire_64, ldaxr, x, uint64_t) > > +#endif > > + > > #ifdef __cplusplus > > } > > #endif > > diff --git a/lib/librte_eal/common/include/generic/rte_pause.h > b/lib/librte_eal/common/include/generic/rte_pause.h > > index 52bd4db..8906473 100644 > > --- a/lib/librte_eal/common/include/generic/rte_pause.h > > +++ b/lib/librte_eal/common/include/generic/rte_pause.h > > @@ -1,5 +1,6 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > * Copyright(c) 2017 Cavium, Inc > > + * Copyright(c) 2019 Arm Limited > > */ > > > > #ifndef _RTE_PAUSE_H_ > > @@ -12,6 +13,10 @@ > > * > > */ > > > > +#include > > +#include > > +#include > > + > > /** > > * Pause CPU execution for a short while > > * > > @@ -20,4 +25,105 @@ > > */ > > static inline void rte_pause(void); > > > > +/** > > + * Wait for *addr to be updated with a 16-bit expected value, with a > relaxed > > + * memory ordering model meaning the loads around this API can be > reordered. > > + * > > + * @param addr > > + * A pointer to the memory location. > > + * @param expected > > + * A 16-bit expected value to be in the memory location. > > + */ > > +__rte_always_inline > > +static void > > +rte_wait_until_equal_relaxed_16(volatile uint16_t *addr, uint16_t > expected); > > + > > +/** > > + * Wait for *addr to be updated with a 32-bit expected value, with a > relaxed > > + * memory ordering model meaning the loads around this API can be > reordered. > > + * > > + * @param addr > > + * A pointer to the memory location. > > + * @param expected > > + * A 32-bit expected value to be in the memory location. > > + */ > > +__rte_always_inline > > +static void > > +rte_wait_until_equal_relaxed_32(volatile uint32_t *addr, uint32_t > expected); > > + > > +/** > > + * Wait for *addr to be updated with a 64-bit expected value, with a > relaxed > > + * memory ordering model meaning the loads around this API can be > reordered. > > + * > > + * @param addr > > + * A pointer to the memory location. > > + * @param expected > > + * A 64-bit expected value to be in the memory location. > > + */ > > +__rte_always_inline > > +static void > > +rte_wait_until_equal_relaxed_64(volatile uint64_t *addr, uint64_t > expected); > > + > > +/** > > + * Wait for *addr to be updated with a 16-bit expected value, with an > acquire > > + * memory ordering model meaning the loads after this API can't be > observed > > + * before this API. > > + * > > + * @param addr > > + * A pointer to the memory location. > > + * @param expected > > + * A 16-bit expected value to be in the memory location. > > + */ > > +__rte_always_inline > > +static void > > +rte_wait_until_equal_acquire_16(volatile uint16_t *addr, uint16_t > expected); > > + > > +/** > > + * Wait for *addr to be updated with a 32-bit expected value, with an > acquire > > + * memory ordering model meaning the loads after this API can't be > observed > > + * before this API. > > + * > > + * @param addr > > + * A pointer to the memory location. > > + * @param expected > > + * A 32-bit expected value to be in the memory location. > > + */ > > +__rte_always_inline > > +static void > > +rte_wait_until_equal_acquire_32(volatile uint32_t *addr, uint32_t > expected); >=20 > LGTM in general. > One stylish thing: wouldn't it be better to have an API like that: > rte_wait_until_equal_acquire_X(addr, expected, memory_order) > ? >=20 > I.E. - pass memorder as parameter, not to incorporate it into function na= me? > Less functions, plus user can specify order himself. > Plus looks similar to C11 atomic instrincts. >=20 Thanks for your comment, will fix this in v8. > > + > > +/** > > + * Wait for *addr to be updated with a 64-bit expected value, with an > acquire > > + * memory ordering model meaning the loads after this API can't be > observed > > + * before this API. > > + * > > + * @param addr > > + * A pointer to the memory location. > > + * @param expected > > + * A 64-bit expected value to be in the memory location. > > + */ > > +__rte_always_inline > > +static void > > +rte_wait_until_equal_acquire_64(volatile uint64_t *addr, uint64_t > expected); > > + > > +#if !defined(RTE_ARM_USE_WFE) > > +#define __WAIT_UNTIL_EQUAL(op_name, size, type, memorder) \ > > +__rte_always_inline \ > > +static void \ > > +rte_wait_until_equal_##op_name##_##size(volatile type *addr, \ > > + type expected) \ > > +{ \ > > + while (__atomic_load_n(addr, memorder) !=3D expected) \ > > + rte_pause(); \ > > +} > > + > > +/* Wait for *addr to be updated with expected value */ > > +__WAIT_UNTIL_EQUAL(relaxed, 16, uint16_t, __ATOMIC_RELAXED) > > +__WAIT_UNTIL_EQUAL(acquire, 16, uint16_t, __ATOMIC_ACQUIRE) > > +__WAIT_UNTIL_EQUAL(relaxed, 32, uint32_t, __ATOMIC_RELAXED) > > +__WAIT_UNTIL_EQUAL(acquire, 32, uint32_t, __ATOMIC_ACQUIRE) > > +__WAIT_UNTIL_EQUAL(relaxed, 64, uint64_t, __ATOMIC_RELAXED) > > +__WAIT_UNTIL_EQUAL(acquire, 64, uint64_t, __ATOMIC_ACQUIRE) > > +#endif /* RTE_ARM_USE_WFE */ > > + > > #endif /* _RTE_PAUSE_H_ */ > > -- > > 2.7.4