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X-Microsoft-Antispam-Message-Info: +84soAO0PLQDK3mpphagSSkx4G/vwoe84yKYkXRsahcg/mAqXHUtvI+jxe3tHIm47bNn81r6DydHVJr0q5Y7CBqW7bLnpw+zLmbZDPH7AspHkfMct82ayB7s8DxM733GP+HdqkNvwZh4LnA6mvPSegj9pPXbgbsVJ+bil2RZi5qID1uNBxWV+C5c5oIK3IREx5dh2zGIOrFV23akt5EGdkkK6fX3D3BA6G6pGB+ULLjP/M1y0kVEqX7lvmNgNz5yWdvez01qugF8rSd6UHTi9ruw7OnZXtq8k6rw/YzQ5W/dt9kDruCvDzksM7NzafNxe/to+ncWRsocFg2N6n/yi4f8ebadjxoX3B2EORoiIF+BPH+rZ2JfdsulYjBMgQCHXROcHp3cMmKr+rx3g4iCdToLK3PAi8hcHsCuP8UvxCn2PaBTULet0iwmuQDniH3lKrkuix36pXVHdBtT/eZiHVsJ0i3zXnwM0zGiPFD1eRzjUPpHLb1RO75Td9W7ZkVdAVUQQXFs5ANV8jgJcGYotg== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2020 07:11:19.4242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e0c20c4-b86c-4da8-6c03-08d7c4c23b54 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB2039 Subject: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Haifeng, > -----Original Message----- > From: dev On Behalf Of Linhaifeng > Sent: Monday, March 9, 2020 5:23 PM > To: dev@dpdk.org; thomas@monjalon.net > Cc: chenchanghu ; xudingke > ; Lilijun (Jerry) > Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 >=20 > We should use isb rather than dsb to sync system counter to cntvct_el0. >=20 > Signed-off-by: Haifeng Lin > --- > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ > lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ > 2 files changed, 5 insertions(+) >=20 > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > index 859ae129d..7e8049725 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > @@ -21,6 +21,7 @@ extern "C" { > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") > #define dmb(opt) asm volatile("dmb " #opt : : : "memory") > +#define isb() asm volatile("isb" : : : "memory") > #define rte_mb() dsb(sy) > @@ -44,6 +45,8 @@ extern "C" { > #define rte_cio_rmb() dmb(oshld) > +#define rte_isb() isb() > + > /*------------------------ 128 bit atomic operations --------------------= -----*/ > #if defined(__ARM_FEATURE_ATOMICS) || > defined(RTE_ARM_FEATURE_ATOMICS) > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > index 68e7c7338..29f524901 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > @@ -18,6 +18,7 @@ extern "C" { > * The time base for this lcore. > */ > #ifndef RTE_ARM_EAL_RDTSC_USE_PMU > + > /** > * This call is portable to any ARMv8 architecture, however, typically > * cntvct_el0 runs at <=3D 100MHz and it may be imprecise for some tasks= . > @@ -27,6 +28,7 @@ rte_rdtsc(void) > { > uint64_t tsc; > + rte_isb(); Good catch, could you add a link to the commit log as a reference. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arc= h/arm64/include/asm/arch_timer.h?h=3Dv5.5#n220 > asm volatile("mrs %0, cntvct_el0" : "=3Dr" (tsc)); In kernel, there is a call to arch_counter_enforce_ordering(cnt), maybe it = is also necessary.=20 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arc= h/arm64/include/asm/arch_timer.h?h=3Dv5.5#n168 > return tsc; > } > --