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DIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR05MB3235; H:AM4PR05MB3265.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: cw9tMw9RoYnBs03SR6MhlEFhOLqqQneITNl9NgyOdgTrcXzWnf+0qo+gKAUziFjL1MyUeW1uhPH8pT4Zd32hGiPoKoD4RLg5deqM3FV6scJiMF/ttmtMqxmln0cs2iElyYnLQYQ9sYG7CYbE45XQwLGJiyzwHS2i9JhWMu2yMRFOyPRw0gEXMCe/0fVU7oFVygGvs4YntvwgMMC8ynfhZhVDGZS+QFqtfgtHOCNb3sy7r7+SUjzADyvuBR71RzyzLke8zc6aBuzRHtDH9bGCZoqWhrJUPrIyHCOG0h9Vvq3cHRNXUdnSb+7alEI5H7lIjWSiTBKDHQN2nQQTvuEp7PGhAeZEgUC3SvZa75ygn5DaYlN0CYSiGChUpu1cfN/EO/hesz9igU0fHIO7tzJt5bwgelS/jcdnzQRx/RD4uTA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4be180ff-d126-4780-825d-08d7042d4d94 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jul 2019 05:21:31.5213 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: viacheslavo@mellanox.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3235 Subject: Re: [dpdk-dev] [Suspected-Phishing][PATCH v7 3/4] net/mlx5: match GRE's key and present bits X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Xiaoyu Min > Sent: Friday, July 5, 2019 12:54 > To: Adrien Mazarguil ; Ori Kam > ; Slava Ovsiienko ; > John McNamara ; Marko Kovacevic > ; Shahaf Shuler ; > Yongseok Koh > Cc: dev@dpdk.org > Subject: [Suspected-Phishing][PATCH v7 3/4] net/mlx5: match GRE's key and > present bits >=20 > support matching on the present bits (C,K,S) as well as the optional key = field. >=20 > If the rte_flow_item_gre_key is specified in pattern, it will set K prese= nt > match automatically. >=20 > Signed-off-by: Xiaoyu Min Acked-by: Viacheslav Ovsiienko > --- > doc/guides/rel_notes/release_19_08.rst | 5 ++ > drivers/net/mlx5/mlx5_flow.c | 61 ++++++++++++++++++- > drivers/net/mlx5/mlx5_flow.h | 6 ++ > drivers/net/mlx5/mlx5_flow_dv.c | 84 ++++++++++++++++++++++++++ > drivers/net/mlx5/mlx5_prm.h | 6 +- > 5 files changed, 160 insertions(+), 2 deletions(-) >=20 > diff --git a/doc/guides/rel_notes/release_19_08.rst > b/doc/guides/rel_notes/release_19_08.rst > index 223479c6d4..1ba551d2a7 100644 > --- a/doc/guides/rel_notes/release_19_08.rst > +++ b/doc/guides/rel_notes/release_19_08.rst > @@ -128,6 +128,11 @@ New Features > Added telemetry mode to l3fwd-power application to report > application level busyness, empty and full polls of rte_eth_rx_burst()= . >=20 > +* **Updated Mellanox mlx5 driver.** > + > + Updated Mellanox mlx5 driver with new features and improvements, > including: > + > + * Added support for matching on GRE's key and C,K,S present bits. >=20 > Removed Items > ------------- > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index 0c6bf4114b..fbae33a768 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -1562,6 +1562,61 @@ mlx5_flow_validate_item_vxlan_gpe(const > struct rte_flow_item *item, > " defined"); > return 0; > } > +/** > + * Validate GRE Key item. > + * > + * @param[in] item > + * Item specification. > + * @param[in] item_flags > + * Bit flags to mark detected items. > + * @param[in] gre_item > + * Pointer to gre_item > + * @param[out] error > + * Pointer to error structure. > + * > + * @return > + * 0 on success, a negative errno value otherwise and rte_errno is set= . > + */ > +int > +mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, > + uint64_t item_flags, > + const struct rte_flow_item *gre_item, > + struct rte_flow_error *error) > +{ > + const rte_be32_t *mask =3D item->mask; > + int ret =3D 0; > + rte_be32_t gre_key_default_mask =3D RTE_BE32(UINT32_MAX); > + const struct rte_flow_item_gre *gre_spec =3D gre_item->spec; > + const struct rte_flow_item_gre *gre_mask =3D gre_item->mask; > + > + if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) > + return rte_flow_error_set(error, ENOTSUP, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "Multiple GRE key not support"); > + if (!(item_flags & MLX5_FLOW_LAYER_GRE)) > + return rte_flow_error_set(error, ENOTSUP, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "No preceding GRE header"); > + if (item_flags & MLX5_FLOW_LAYER_INNER) > + return rte_flow_error_set(error, ENOTSUP, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "GRE key following a wrong item"); > + if (!gre_mask) > + gre_mask =3D &rte_flow_item_gre_mask; > + if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && > + !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "Key bit must be on"); > + > + if (!mask) > + mask =3D &gre_key_default_mask; > + ret =3D mlx5_flow_item_acceptable > + (item, (const uint8_t *)mask, > + (const uint8_t *)&gre_key_default_mask, > + sizeof(rte_be32_t), error); > + return ret; > +} >=20 > /** > * Validate GRE item. > @@ -1587,6 +1642,10 @@ mlx5_flow_validate_item_gre(const struct > rte_flow_item *item, > const struct rte_flow_item_gre *spec __rte_unused =3D item->spec; > const struct rte_flow_item_gre *mask =3D item->mask; > int ret; > + const struct rte_flow_item_gre nic_mask =3D { > + .c_rsvd0_ver =3D RTE_BE16(0xB000), > + .protocol =3D RTE_BE16(UINT16_MAX), > + }; >=20 > if (target_protocol !=3D 0xff && target_protocol !=3D IPPROTO_GRE) > return rte_flow_error_set(error, EINVAL, @@ -1606,7 > +1665,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item > *item, > mask =3D &rte_flow_item_gre_mask; > ret =3D mlx5_flow_item_acceptable > (item, (const uint8_t *)mask, > - (const uint8_t *)&rte_flow_item_gre_mask, > + (const uint8_t *)&nic_mask, > sizeof(struct rte_flow_item_gre), error); > if (ret < 0) > return ret; > diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h > index 65cfdbda9f..4439f30d8e 100644 > --- a/drivers/net/mlx5/mlx5_flow.h > +++ b/drivers/net/mlx5/mlx5_flow.h > @@ -50,6 +50,8 @@ > #define MLX5_FLOW_ITEM_METADATA (1u << 16) #define > MLX5_FLOW_ITEM_PORT_ID (1u << 17) >=20 > +#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18) > + > /* Outer Masks. */ > #define MLX5_FLOW_LAYER_OUTER_L3 \ > (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | > MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -462,6 +464,10 @@ int > mlx5_flow_validate_item_gre(const struct rte_flow_item *item, > uint64_t item_flags, > uint8_t target_protocol, > struct rte_flow_error *error); > +int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, > + uint64_t item_flags, > + const struct rte_flow_item *gre_item, > + struct rte_flow_error *error); > int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, > uint64_t item_flags, > const struct rte_flow_item_ipv4 *acc_mask, > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 933ad0b819..16600c8f8e 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -2066,6 +2066,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const > struct rte_flow_attr *attr, > uint64_t last_item =3D 0; > uint8_t next_protocol =3D 0xff; > int actions_n =3D 0; > + const struct rte_flow_item *gre_item =3D NULL; > struct rte_flow_item_tcp nic_tcp_mask =3D { > .hdr =3D { > .tcp_flags =3D 0xFF, > @@ -2175,8 +2176,16 @@ flow_dv_validate(struct rte_eth_dev *dev, const > struct rte_flow_attr *attr, > next_protocol, > error); > if (ret < 0) > return ret; > + gre_item =3D items; > last_item =3D MLX5_FLOW_LAYER_GRE; > break; > + case RTE_FLOW_ITEM_TYPE_GRE_KEY: > + ret =3D mlx5_flow_validate_item_gre_key > + (items, item_flags, gre_item, error); > + if (ret < 0) > + return ret; > + item_flags |=3D MLX5_FLOW_LAYER_GRE_KEY; > + break; > case RTE_FLOW_ITEM_TYPE_VXLAN: > ret =3D mlx5_flow_validate_item_vxlan(items, > item_flags, > error); > @@ -2922,6 +2931,45 @@ flow_dv_translate_item_udp(void *matcher, > void *key, > rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m- > >hdr.dst_port)); } >=20 > +/** > + * Add GRE optional Key item to matcher and to the value. > + * > + * @param[in, out] matcher > + * Flow matcher. > + * @param[in, out] key > + * Flow matcher value. > + * @param[in] item > + * Flow pattern to translate. > + * @param[in] inner > + * Item is inner pattern. > + */ > +static void > +flow_dv_translate_item_gre_key(void *matcher, void *key, > + const struct rte_flow_item *item) { > + const rte_be32_t *key_m =3D item->mask; > + const rte_be32_t *key_v =3D item->spec; > + void *misc_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > misc_parameters); > + void *misc_v =3D MLX5_ADDR_OF(fte_match_param, key, > misc_parameters); > + rte_be32_t gre_key_default_mask =3D RTE_BE32(UINT32_MAX); > + > + if (!key_v) > + return; > + if (!key_m) > + key_m =3D &gre_key_default_mask; > + /* GRE K bit must be on and should already be validated */ > + MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1); > + MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1); > + MLX5_SET(fte_match_set_misc, misc_m, gre_key_h, > + rte_be_to_cpu_32(*key_m) >> 8); > + MLX5_SET(fte_match_set_misc, misc_v, gre_key_h, > + rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8); > + MLX5_SET(fte_match_set_misc, misc_m, gre_key_l, > + rte_be_to_cpu_32(*key_m) & 0xFF); > + MLX5_SET(fte_match_set_misc, misc_v, gre_key_l, > + rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF); } > + > /** > * Add GRE item to matcher and to the value. > * > @@ -2945,6 +2993,20 @@ flow_dv_translate_item_gre(void *matcher, void > *key, > void *headers_v; > void *misc_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > misc_parameters); > void *misc_v =3D MLX5_ADDR_OF(fte_match_param, key, > misc_parameters); > + struct { > + union { > + __extension__ > + struct { > + uint16_t version:3; > + uint16_t rsvd0:9; > + uint16_t s_present:1; > + uint16_t k_present:1; > + uint16_t rsvd_bit1:1; > + uint16_t c_present:1; > + }; > + uint16_t value; > + }; > + } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v; >=20 > if (inner) { > headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > @@ -2965,6 +3027,23 @@ flow_dv_translate_item_gre(void *matcher, void > *key, > rte_be_to_cpu_16(gre_m->protocol)); > MLX5_SET(fte_match_set_misc, misc_v, gre_protocol, > rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol)); > + gre_crks_rsvd0_ver_m.value =3D rte_be_to_cpu_16(gre_m- > >c_rsvd0_ver); > + gre_crks_rsvd0_ver_v.value =3D rte_be_to_cpu_16(gre_v- > >c_rsvd0_ver); > + MLX5_SET(fte_match_set_misc, misc_m, gre_c_present, > + gre_crks_rsvd0_ver_m.c_present); > + MLX5_SET(fte_match_set_misc, misc_v, gre_c_present, > + gre_crks_rsvd0_ver_v.c_present & > + gre_crks_rsvd0_ver_m.c_present); > + MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, > + gre_crks_rsvd0_ver_m.k_present); > + MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, > + gre_crks_rsvd0_ver_v.k_present & > + gre_crks_rsvd0_ver_m.k_present); > + MLX5_SET(fte_match_set_misc, misc_m, gre_s_present, > + gre_crks_rsvd0_ver_m.s_present); > + MLX5_SET(fte_match_set_misc, misc_v, gre_s_present, > + gre_crks_rsvd0_ver_v.s_present & > + gre_crks_rsvd0_ver_m.s_present); > } >=20 > /** > @@ -3995,6 +4074,11 @@ flow_dv_translate(struct rte_eth_dev *dev, > items, tunnel); > last_item =3D MLX5_FLOW_LAYER_GRE; > break; > + case RTE_FLOW_ITEM_TYPE_GRE_KEY: > + flow_dv_translate_item_gre_key(match_mask, > + match_value, items); > + item_flags |=3D MLX5_FLOW_LAYER_GRE_KEY; > + break; > case RTE_FLOW_ITEM_TYPE_NVGRE: > flow_dv_translate_item_nvgre(match_mask, > match_value, > items, tunnel); > diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h > index 1a199580c5..4022770b7b 100644 > --- a/drivers/net/mlx5/mlx5_prm.h > +++ b/drivers/net/mlx5/mlx5_prm.h > @@ -416,7 +416,11 @@ typedef uint8_t u8; #define > MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) >=20 > struct mlx5_ifc_fte_match_set_misc_bits { > - u8 reserved_at_0[0x8]; > + u8 gre_c_present[0x1]; > + u8 reserved_at_1[0x1]; > + u8 gre_k_present[0x1]; > + u8 gre_s_present[0x1]; > + u8 source_vhci_port[0x4]; > u8 source_sqn[0x18]; > u8 reserved_at_20[0x10]; > u8 source_port[0x10]; > -- > 2.21.0