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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 02887982-a5d2-46a0-bbd4-08d7ad8b4573 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Feb 2020 18:09:57.1667 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: h6DLCJAdVNhBM+qcm7zZbVC+4WXqq0Ws1VY1KZduF3uH9XKuWra8RXVnZxQDleZ+zXkKwXt5XPTxr50aKqJ8D231SgmE3te7toJPXa7G8QQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3220 Subject: Re: [dpdk-dev] [PATCH] net/mlx5: set VLAN tag matcher bit properly X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Dekel Peled > Sent: Sunday, February 9, 2020 14:26 > To: Matan Azrad ; Slava Ovsiienko > ; Raslan Darawsheh > Cc: dev@dpdk.org > Subject: [PATCH] net/mlx5: set VLAN tag matcher bit properly >=20 > Currently MLX5 PMD can't match on untagged packets specifically. > Tagged traffic still hits the flows intended for untagged packets. > If the flow has ETH, it will catch all matching packets, tagged and untag= ged. > The solution is to use cvlan_tag bit. > If mask=3D1 and value=3D0 it matches on untagged traffic. > If mask=3D1 and value=3D1 it matches on tagged traffic. > This is the kernel implementation. >=20 > This patch updated MLX5 PMD to set cvlan_tag mask and value according to > flow rule contents. >=20 > Signed-off-by: Dekel Peled Acked-by: Viacheslav Ovsiienko > --- > drivers/net/mlx5/mlx5_flow_dv.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 3daabd3..a28af7c 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -5214,6 +5214,15 @@ struct field_modify_info modify_tcp[] =3D { > rte_be_to_cpu_16(eth_m->type)); > l24_v =3D MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, > ethertype); > *(uint16_t *)(l24_v) =3D eth_m->type & eth_v->type; > + if (eth_v->type) { > + /* When ethertype is present set mask for tagged VLAN. */ > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); > + /* Set value for tagged VLAN if ethertype is 802.1Q. */ > + if (eth_v->type =3D=3D RTE_BE16(RTE_ETHER_TYPE_VLAN) || > + eth_v->type =3D=3D RTE_BE16(RTE_ETHER_TYPE_QINQ)) > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, > cvlan_tag, > + 1); > + } > } >=20 > /** > @@ -5354,6 +5363,7 @@ struct field_modify_info modify_tcp[] =3D { > ipv4_m->hdr.next_proto_id); > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id); > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); > } >=20 > /** > @@ -5458,6 +5468,7 @@ struct field_modify_info modify_tcp[] =3D { > ipv6_m->hdr.proto); > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > ipv6_v->hdr.proto & ipv6_m->hdr.proto); > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); > } >=20 > /** > -- > 1.8.3.1