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SCL:1; SRVR:AM4PR05MB3505; H:AM4PR05MB3265.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: oGjLa3y9lkZHP58GmtNyfzXsMCZBuUDP+C7Fp3Ojv/6AaacL0vLw2M+ySOTxaj8eYZ1uL0jz+KHUM5iPl0DFGPLcdjCpmpmO8E6GKtV3TT9T0kNdrClKcngMHl06t3ehdR3HLoi/agN1+BEShk2K/LfkFiZdb0fDzclhr7vXQBrL0tAWjNuzKvYyuYW2QQSRKJwLB81jGWTaRLuFEpy3Vmz8eNyCQgaR+SBZgUVQHpejFzDcTYlAtUWzgWx+zZ1NMDFIxp9R+6ixfc7Nw5ZwjmfJDRY4cf0lBJKE24yKNoPxSzltybfuv/+iDEF2yPz7ZS5WfUbXjzXEDl/gOReclGN4RvX/QcSysOomHU06+mg58d+Bfo+G8S8lZS0gn/cx/2e3whXas9Y0sL/osIhnv8QBfe7yjIgB1k+eORlInCA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 49d172f6-a8d6-4b28-daea-08d7189f34b4 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Aug 2019 05:47:15.6570 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: viacheslavo@mellanox.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3505 Subject: Re: [dpdk-dev] [Suspected-Phishing][PATCH] net/mlx5: fix VLAN inner type matching on DR/DV X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Xiaoyu Min > Sent: Friday, August 2, 2019 12:18 > To: Shahaf Shuler ; Yongseok Koh > ; Slava Ovsiienko > Cc: dev@dpdk.org; Ori Kam > Subject: [Suspected-Phishing][PATCH] net/mlx5: fix VLAN inner type > matching on DR/DV >=20 > The rte_flow_item_vlan has the inner_type, which is missing on DR/DV flow > engine. >=20 > By adding this support, the example testpmd commands could be: >=20 > - matching all vlan traffic with id 2: >=20 > testpmd> flow create 0 ingress pattern eth / vlan vid is 2 / end > actions queue index 2 / end >=20 > - matching all ipv4 traffic in vlan with id 2: >=20 > testpmd> flow create 0 ingress pattern eth / vlan vid is 2 > inner_type is 0x0800 / end actions queue index 2 / end >=20 > Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items") > Cc: orika@mellanox.com >=20 > Signed-off-by: Xiaoyu Min Acked-by: Viacheslav Ovsiienko > --- > drivers/net/mlx5/mlx5_flow_dv.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 9c0a2613d5..f786c7a2c4 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -3469,10 +3469,6 @@ flow_dv_translate_item_vlan(struct mlx5_flow > *dev_flow, { > const struct rte_flow_item_vlan *vlan_m =3D item->mask; > const struct rte_flow_item_vlan *vlan_v =3D item->spec; > - const struct rte_flow_item_vlan nic_mask =3D { > - .tci =3D RTE_BE16(0x0fff), > - .inner_type =3D RTE_BE16(0xffff), > - }; > void *headers_m; > void *headers_v; > uint16_t tci_m; > @@ -3481,7 +3477,7 @@ flow_dv_translate_item_vlan(struct mlx5_flow > *dev_flow, > if (!vlan_v) > return; > if (!vlan_m) > - vlan_m =3D &nic_mask; > + vlan_m =3D &rte_flow_item_vlan_mask; > if (inner) { > headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > inner_headers); > @@ -3507,6 +3503,10 @@ flow_dv_translate_item_vlan(struct mlx5_flow > *dev_flow, > MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12); > MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> > 13); > MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> > 13); > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, > + rte_be_to_cpu_16(vlan_m->inner_type)); > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, > + rte_be_to_cpu_16(vlan_m->inner_type & vlan_v- > >inner_type)); > } >=20 > /** > -- > 2.21.0