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DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: fT5WtGwFHF1e3n/JgxBM7UejZqIfLKfIuq0nBNzoSbczroRIlRA/JFH4yf30tZKxcbuuBI38+nYqHs15QZkrkjjvVTzYQD4WtbG/ZAIvVCYyLrRO1bO3c9L7YC1yMHukfDNR0Mz8vATBd72roue+7JX4t+r2Ebtjj2EzPo3ZVe46TzrWYqyrjkIXsQ9yz7w4qvcg6ebmeF2vVqguLIZiB4gXbA4TqaYEgPwAuDiJq8bDMilK+YoiX/uot8s+OwJnKX5Nv/fnxwR+5L8tsYl48q7pa/CEfQE5R7gZ2nYNLYOtZ5PZtMHZAwJ2bsUnd5HI5zFeTToCLk4ctm2/+NU/9wgjDFoidSI54qF3nF6/zU7mkVWo2RxEGqbghv7U4OAWV/HPxGiNo5reU892DiLhtyam36wvsa/HuDOgkweDUH5ck0nmtbydmvCp4OZ/0NCFFxdh+O6yDre2ZjiTAxQSeIx7D4xIHesCLxfXehsozSc= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM4PR05MB3265.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5aa751c0-b443-4841-3c7d-08d82a63a050 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2020 15:11:05.0378 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JSJhmKkkmV4BmEZxkDGUUYoDfSzTyO3AicrpPBEUkDWh+E4gUVCqM4oLnAp/BbEeRgSi+rCK5uCsz/MX0WhWiZr2RirxvrElBmwfEDASuAg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3155 Subject: Re: [dpdk-dev] [PATCH 3/3] common/mlx5: fix DevX register access opcode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Thomas Monjalon > Sent: Friday, July 17, 2020 18:06 > To: Slava Ovsiienko > Cc: dev@dpdk.org; Matan Azrad ; Raslan > Darawsheh > Subject: Re: [PATCH 3/3] common/mlx5: fix DevX register access opcode >=20 > 17/07/2020 16:28, Viacheslav Ovsiienko: > > The dedicated MLX5_CMD_OP_ACCESS_REGISTER_USER opcode must be > used to > > read hardware register content from unprotected mode. >=20 > Otherwise? What was broken? Otherwise the MLX5_CMD_OP_ACCESS_REGISTER was used, it returned EINVAL and register value was not read. It was supposed to enable ACCESS_REGISTER operation from user mode in kernel driver to read registers, but eventually it was replaced with ACCESS_REGISTER_USER dedicated operation. mlx5 PMD does not rely on this feature strongly, if register reading fails it deduces the timestamp mode from reported timestamp counter frequency. With best regards, Slava