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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: d9f9d054-bce6-43bf-ff23-08d74bd3f2b8 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Oct 2019 09:43:17.8027 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: sathME1PAAKHtw8B0BrivRb4fhqtw0MqtQzV+8Js/01ZIProTKPhmLJ/Vrzo1f5X6pvHvY5ZAx7yGTFBAeg8XZL/BOfoogrjnXmDRiK+idg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3204 Subject: Re: [dpdk-dev] [PATCH v2] net/mlx5: improve validation of item order X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Xiaoyu Min > Sent: Wednesday, September 11, 2019 11:46 > To: Matan Azrad ; Shahaf Shuler > ; Slava Ovsiienko > Cc: dev@dpdk.org; Ori Kam ; stable@dpdk.org > Subject: [PATCH v2] net/mlx5: improve validation of item order >=20 > The Item order validation between L2 and L3 is missing, which leading to = the > following flow rule is accepted: >=20 > testpmd> flow create 0 ingress pattern ipv4 / eth / end actions drop / > end >=20 > Only the outer L3 layer should check whether the L2 layer is present, bec= ause > the L3 layer could directly follow the tunnel layer without L2 layer. >=20 > Meanwhile inner L2 layer should check whether there is inner L3 layer bef= ore > it. >=20 > Fixes: 23c1d42c7138 ("net/mlx5: split flow validation to dedicated functi= on") > Cc: stable@dpdk.org >=20 > Signed-off-by: Xiaoyu Min Acked-by: Viacheslav Ovsiienko > --- > drivers/net/mlx5/mlx5_flow.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index eb360525da..45bd9c8025 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -1224,6 +1224,11 @@ mlx5_flow_validate_item_eth(const struct > rte_flow_item *item, > return rte_flow_error_set(error, ENOTSUP, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "multiple L2 layers not supported"); > + if (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "inner L2 layer should not " > + "follow inner L3 layers"); > if (!mask) > mask =3D &rte_flow_item_eth_mask; > ret =3D mlx5_flow_item_acceptable(item, (const uint8_t *)mask, @@ - > 1270,6 +1275,8 @@ mlx5_flow_validate_item_vlan(const struct > rte_flow_item *item, > const uint64_t vlanm =3D tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : > MLX5_FLOW_LAYER_OUTER_VLAN; >=20 > + const uint64_t l2m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L2 : > + MLX5_FLOW_LAYER_OUTER_L2; > if (item_flags & vlanm) > return rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > @@ -1278,6 +1285,10 @@ mlx5_flow_validate_item_vlan(const struct > rte_flow_item *item, > return rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "L2 layer cannot follow L3/L4 > layer"); > + else if ((item_flags & l2m) =3D=3D 0) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "no L2 layer before VLAN"); > if (!mask) > mask =3D &rte_flow_item_vlan_mask; > ret =3D mlx5_flow_item_acceptable(item, (const uint8_t *)mask, @@ - > 1390,6 +1401,10 @@ mlx5_flow_validate_item_ipv4(const struct > rte_flow_item *item, > return rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "L3 cannot follow an NVGRE > layer."); > + else if (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L2)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "no L2 layer before IPV4"); > if (!mask) > mask =3D &rte_flow_item_ipv4_mask; > else if (mask->hdr.next_proto_id !=3D 0 && @@ -1481,6 +1496,10 @@ > mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, > return rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "L3 cannot follow an NVGRE > layer."); > + else if (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L2)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "no L2 layer before IPV6"); > if (!mask) > mask =3D &rte_flow_item_ipv6_mask; > ret =3D mlx5_flow_item_acceptable(item, (const uint8_t *)mask, > -- > 2.23.0