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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(346002)(376002)(396003)(136003)(39860400002)(46966006)(36840700001)(82310400003)(2906002)(70206006)(33656002)(70586007)(36860700001)(47076005)(81166007)(52536014)(4326008)(5660300002)(86362001)(83380400001)(7696005)(356005)(8676002)(9686003)(186003)(316002)(8936002)(478600001)(55016002)(966005)(336012)(26005)(54906003)(53546011)(110136005)(82740400003)(6506007); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2021 08:24:51.2563 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1916fc4-41dc-409a-bb5a-08d91b68bd17 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT006.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4507 Subject: Re: [dpdk-dev] [PATCH v6 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Chengwen Feng > Sent: Wednesday, May 19, 2021 9:26 PM > To: thomas@monjalon.net; ferruh.yigit@intel.com > Cc: dev@dpdk.org; jerinj@marvell.com; Ruifeng Wang > ; viktorin@rehivetech.com; > bruce.richardson@intel.com; Honnappa Nagarahalli > ; jerinjacobk@gmail.com; > juraj.linkes@pantheon.tech; nd > Subject: [PATCH v6 2/2] net/hns3: refactor SVE code compile method >=20 > Currently, the SVE code is compiled only when -march supports SVE (e.g. '= - > march=3Darmv8.2a+sve'), there maybe some problem[1] with this approach. >=20 > The solution: > a. If the minimum instruction set support SVE then compiles it. > b. Else if the compiler support SVE then compiles it. > c. Otherwise don't compile it. >=20 > [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html >=20 > Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") > Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") > Cc: stable@dpdk.org >=20 > Signed-off-by: Chengwen Feng > --- > drivers/net/hns3/hns3_rxtx.c | 2 +- > drivers/net/hns3/meson.build | 21 ++++++++++++++++++++- > 2 files changed, 21 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c > index 1d7a769..4ef20c6 100644 > --- a/drivers/net/hns3/hns3_rxtx.c > +++ b/drivers/net/hns3/hns3_rxtx.c > @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) > static bool > hns3_get_sve_support(void) > { > -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) > +#if defined(CC_SVE_SUPPORT) > if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) > return false; > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) > diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build > index 53c7df7..5f9af9b 100644 > --- a/drivers/net/hns3/meson.build > +++ b/drivers/net/hns3/meson.build > @@ -35,7 +35,26 @@ deps +=3D ['hash'] >=20 > if arch_subdir =3D=3D 'arm' and dpdk_conf.get('RTE_ARCH_64') > sources +=3D files('hns3_rxtx_vec.c') > - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) !=3D '' > + > + # compile SVE when: > + # a. support SVE in minimum instruction set baseline > + # b. it's not minimum instruction set, but compiler support > + if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) !=3D '' an= d > cc.check_header('arm_sve.h') > + cflags +=3D ['-DCC_SVE_SUPPORT'] With SVE build fix patch [1], CC_SVE_ACLE_SUPPORT will be defined. Here we can use CC_SVE_ACLE_SUPPORT and not to add a new one. [1] http://patches.dpdk.org/project/dpdk/patch/1621495007-28387-1-git-send-= email-fengchengwen@huawei.com/ > sources +=3D files('hns3_rxtx_vec_sve.c') > + elif cc.has_argument('-march=3Darmv8.2-a+sve') and > cc.check_header('arm_sve.h') > + sve_cflags =3D ['-DCC_SVE_SUPPORT'] > + foreach flag: cflags > + # filterout -march -mcpu -mtune > + if not (flag.startswith('-march=3D') or flag.startswith('-mc= pu=3D') or > flag.startswith('-mtune=3D')) > + sve_cflags +=3D flag > + endif > + endforeach > + hns3_sve_lib =3D static_library('hns3_sve_lib', > + 'hns3_rxtx_vec_sve.c', > + dependencies: [static_rte_ethdev], > + include_directories: includes, > + c_args: [sve_cflags, '-march=3Darmv8.2-a+sve']) > + objs +=3D hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') > endif > endif > -- > 2.8.1