[dpdk-dev] [PATCH 0/2] bugfix for SVE compile

[dpdk-dev] [PATCH 0/2] bugfix for SVE compile

[Chengwen Feng]

This patch set contains two bugfixes for SVE compile.
Note:
1) Because 2/2 patch needs backport to 20.11 so we separate it.
2) These two patches already acked by ARM guys from previous threads.

Chengwen Feng (2):
  build: fix SVE compile error with gcc8.3
  net/hns3: fix SVE code compile error with gcc8.3

 config/arm/meson.build         |  6 ++++++
 drivers/net/hns3/hns3_rxtx.c   |  2 +-
 drivers/net/hns3/meson.build   | 20 +++++++++++++++++++-
 lib/eal/arm/include/rte_vect.h |  2 +-
 lib/lpm/rte_lpm.h              |  2 +-
 5 files changed, 28 insertions(+), 4 deletions(-)

-- 
2.8.1

[dpdk-dev] [PATCH 1/2] build: fix SVE compile error with gcc8.3

[Chengwen Feng]

If the target machine has SVE feature (e.g. "-march=armv8.2-a+sve'),
and the compiler are gcc8.3, it will compile error:
	In file included from ../dpdk-next-net/lib/eal/common/
	eal_common_options.c:38:
	../dpdk-next-net/lib/eal/arm/include/rte_vect.h:13:10: fatal
	error: arm_sve.h: No such file or directory
	#include <arm_sve.h>
	       ^~~~~~~~~~~
	compilation terminated.

The root cause is that gcc8.3 supports SVE (the macro
__ARM_FEATURE_SVE was 1), but it doesn't support SVE ACLE [1].

The solution:
a) Detect compiler whether support SVE ACLE, if support then define
RTE_HAS_SVE_ACLE macro.
b) Use the RTE_HAS_SVE_ACLE macro to include SVE header file.

[1] ACLE:  Arm C Language Extensions, the SVE ACLE header file is
<arm_sve.h>, user should include it when writing ACLE SVE code.

Fixes: 67b68824a82d ("lpm/arm: support SVE")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 config/arm/meson.build         | 6 ++++++
 lib/eal/arm/include/rte_vect.h | 2 +-
 lib/lpm/rte_lpm.h              | 2 +-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index e83a56e..7342626 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -488,3 +488,9 @@ if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
     compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
     'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 endif
+
+# Check whether SVE ACLE is supported and set the corresponding flag which will used with SVE ACLE code.
+if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
+        cc.check_header('arm_sve.h'))
+    dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
+endif
diff --git a/lib/eal/arm/include/rte_vect.h b/lib/eal/arm/include/rte_vect.h
index 093e912..4b705ba 100644
--- a/lib/eal/arm/include/rte_vect.h
+++ b/lib/eal/arm/include/rte_vect.h
@@ -9,7 +9,7 @@
 #include "generic/rte_vect.h"
 #include "rte_debug.h"
 #include "arm_neon.h"
-#ifdef __ARM_FEATURE_SVE
+#ifdef RTE_HAS_SVE_ACLE
 #include <arm_sve.h>
 #endif
 
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 28b5768..5eb14c1 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -402,7 +402,7 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
 	uint32_t defv);
 
 #if defined(RTE_ARCH_ARM)
-#ifdef __ARM_FEATURE_SVE
+#ifdef RTE_HAS_SVE_ACLE
 #include "rte_lpm_sve.h"
 #else
 #include "rte_lpm_neon.h"
-- 
2.8.1

[dpdk-dev] [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3

[Chengwen Feng]

If the target machine has SVE feature (e.g. '-march=armv8.2-a+sve'),
and compiler are gcc8.3, it will compile error, the error is arm_sve.h
no such file or directory.

The solution:
a. If RTE_HAS_SVE_ACLE defined (it means the minimum instruction set
support SVE ACLE) then compiles it.
b. Else if the compiler support SVE ACLE then compiles it.
c. Otherwise don't compile it.

Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx")
Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx")
Cc: stable@dpdk.org

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 drivers/net/hns3/hns3_rxtx.c |  2 +-
 drivers/net/hns3/meson.build | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
index cb9eccf..a86e105 100644
--- a/drivers/net/hns3/hns3_rxtx.c
+++ b/drivers/net/hns3/hns3_rxtx.c
@@ -2811,7 +2811,7 @@ hns3_get_default_vec_support(void)
 static bool
 hns3_get_sve_support(void)
 {
-#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
+#if defined(RTE_HAS_SVE_ACLE)
 	if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
 		return false;
 	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build
index 53c7df7..a99e0db 100644
--- a/drivers/net/hns3/meson.build
+++ b/drivers/net/hns3/meson.build
@@ -35,7 +35,25 @@ deps += ['hash']
 
 if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64')
     sources += files('hns3_rxtx_vec.c')
-    if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
+
+    # compile SVE when:
+    # a. support SVE in minimum instruction set baseline
+    # b. it's not minimum instruction set, but compiler support
+    if dpdk_conf.has('RTE_HAS_SVE_ACLE')
         sources += files('hns3_rxtx_vec_sve.c')
+    elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h')
+        cflags += ['-DRTE_HAS_SVE_ACLE=1']
+        sve_cflags = []
+        foreach flag: cflags
+            if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune='))
+                sve_cflags += flag
+            endif
+        endforeach
+        hns3_sve_lib = static_library('hns3_sve_lib',
+                        'hns3_rxtx_vec_sve.c',
+                        dependencies: [static_rte_ethdev],
+                        include_directories: includes,
+                        c_args: [sve_cflags, '-march=armv8.2-a+sve'])
+        objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c')
     endif
 endif
-- 
2.8.1

Re: [dpdk-dev] [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3

[Ruifeng Wang]

> -----Original Message-----
> From: Chengwen Feng <fengchengwen@huawei.com>
> Sent: Monday, June 28, 2021 10:58 AM
> To: thomas@monjalon.net; ferruh.yigit@intel.com; Ruifeng Wang
> <Ruifeng.Wang@arm.com>
> Cc: dev@dpdk.org; bruce.richardson@intel.com;
> vladimir.medvedkin@intel.com; viktorin@rehivetech.com;
> jerinj@marvell.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; jerinjacobk@gmail.com;
> juraj.linkes@pantheon.tech
> Subject: [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3
> 
> If the target machine has SVE feature (e.g. '-march=armv8.2-a+sve'), and
> compiler are gcc8.3, it will compile error, the error is arm_sve.h no such file or
> directory.
> 
> The solution:
> a. If RTE_HAS_SVE_ACLE defined (it means the minimum instruction set
> support SVE ACLE) then compiles it.
> b. Else if the compiler support SVE ACLE then compiles it.
> c. Otherwise don't compile it.
> 
> Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx")
> Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
> Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
> ---
>  drivers/net/hns3/hns3_rxtx.c |  2 +-
>  drivers/net/hns3/meson.build | 20 +++++++++++++++++++-
>  2 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
> index cb9eccf..a86e105 100644
> --- a/drivers/net/hns3/hns3_rxtx.c
> +++ b/drivers/net/hns3/hns3_rxtx.c
> @@ -2811,7 +2811,7 @@ hns3_get_default_vec_support(void)
>  static bool
>  hns3_get_sve_support(void)
>  {
> -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
> +#if defined(RTE_HAS_SVE_ACLE)
>  	if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
>  		return false;
>  	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
> diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build
> index 53c7df7..a99e0db 100644
> --- a/drivers/net/hns3/meson.build
> +++ b/drivers/net/hns3/meson.build
> @@ -35,7 +35,25 @@ deps += ['hash']
> 
>  if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64')
>      sources += files('hns3_rxtx_vec.c')
> -    if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> +
> +    # compile SVE when:
> +    # a. support SVE in minimum instruction set baseline
> +    # b. it's not minimum instruction set, but compiler support
> +    if dpdk_conf.has('RTE_HAS_SVE_ACLE')
>          sources += files('hns3_rxtx_vec_sve.c')
> +    elif cc.has_argument('-march=armv8.2-a+sve') and
> cc.check_header('arm_sve.h')
> +        cflags += ['-DRTE_HAS_SVE_ACLE=1']
> +        sve_cflags = []
Global cflags will be changed here. I think it is not very good as build of other parts could be without SVE support.
How about " sve_cflags = ['-DRTE_HAS_SVE_ACLE=1']" and drop changes to cflags?
In this way, the additional flag will be limited to hns3_sve_lib.

> +        foreach flag: cflags
> +            if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or
> flag.startswith('-mtune='))
> +                sve_cflags += flag
> +            endif
> +        endforeach
> +        hns3_sve_lib = static_library('hns3_sve_lib',
> +                        'hns3_rxtx_vec_sve.c',
> +                        dependencies: [static_rte_ethdev],
> +                        include_directories: includes,
> +                        c_args: [sve_cflags, '-march=armv8.2-a+sve'])
> +        objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c')
>      endif
>  endif
> --
> 2.8.1

Re: [dpdk-dev] [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3

[fengchengwen]

On 2021/6/28 11:33, Ruifeng Wang wrote:
>> -----Original Message-----
>> From: Chengwen Feng <fengchengwen@huawei.com>
>> Sent: Monday, June 28, 2021 10:58 AM
>> To: thomas@monjalon.net; ferruh.yigit@intel.com; Ruifeng Wang
>> <Ruifeng.Wang@arm.com>
>> Cc: dev@dpdk.org; bruce.richardson@intel.com;
>> vladimir.medvedkin@intel.com; viktorin@rehivetech.com;
>> jerinj@marvell.com; Honnappa Nagarahalli
>> <Honnappa.Nagarahalli@arm.com>; jerinjacobk@gmail.com;
>> juraj.linkes@pantheon.tech
>> Subject: [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3
>>
>> If the target machine has SVE feature (e.g. '-march=armv8.2-a+sve'), and
>> compiler are gcc8.3, it will compile error, the error is arm_sve.h no such file or
>> directory.
>>
>> The solution:
>> a. If RTE_HAS_SVE_ACLE defined (it means the minimum instruction set
>> support SVE ACLE) then compiles it.
>> b. Else if the compiler support SVE ACLE then compiles it.
>> c. Otherwise don't compile it.
>>
>> Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx")
>> Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx")
>> Cc: stable@dpdk.org
>>
>> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
>> Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
>> ---
>>  drivers/net/hns3/hns3_rxtx.c |  2 +-
>>  drivers/net/hns3/meson.build | 20 +++++++++++++++++++-
>>  2 files changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
>> index cb9eccf..a86e105 100644
>> --- a/drivers/net/hns3/hns3_rxtx.c
>> +++ b/drivers/net/hns3/hns3_rxtx.c
>> @@ -2811,7 +2811,7 @@ hns3_get_default_vec_support(void)
>>  static bool
>>  hns3_get_sve_support(void)
>>  {
>> -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
>> +#if defined(RTE_HAS_SVE_ACLE)
>>  	if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
>>  		return false;
>>  	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
>> diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build
>> index 53c7df7..a99e0db 100644
>> --- a/drivers/net/hns3/meson.build
>> +++ b/drivers/net/hns3/meson.build
>> @@ -35,7 +35,25 @@ deps += ['hash']
>>
>>  if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64')
>>      sources += files('hns3_rxtx_vec.c')
>> -    if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
>> +
>> +    # compile SVE when:
>> +    # a. support SVE in minimum instruction set baseline
>> +    # b. it's not minimum instruction set, but compiler support
>> +    if dpdk_conf.has('RTE_HAS_SVE_ACLE')
>>          sources += files('hns3_rxtx_vec_sve.c')
>> +    elif cc.has_argument('-march=armv8.2-a+sve') and
>> cc.check_header('arm_sve.h')
>> +        cflags += ['-DRTE_HAS_SVE_ACLE=1']
>> +        sve_cflags = []
> Global cflags will be changed here. I think it is not very good as build of other parts could be without SVE support.
> How about " sve_cflags = ['-DRTE_HAS_SVE_ACLE=1']" and drop changes to cflags?
> In this way, the additional flag will be limited to hns3_sve_lib.

This will not change global cflags: the cflags was independent from other drives [implemented in drivers/meson.build]
And I also check the 'build.ninja' and found the RTE_HAS_SVE_ACLE only defined with hns3 driver source file.
PS: hns3_rxtx.c also refer the marco 'RTE_HAS_SVE_ACLE'.

> 
>> +        foreach flag: cflags
>> +            if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or
>> flag.startswith('-mtune='))
>> +                sve_cflags += flag
>> +            endif
>> +        endforeach
>> +        hns3_sve_lib = static_library('hns3_sve_lib',
>> +                        'hns3_rxtx_vec_sve.c',
>> +                        dependencies: [static_rte_ethdev],
>> +                        include_directories: includes,
>> +                        c_args: [sve_cflags, '-march=armv8.2-a+sve'])
>> +        objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c')
>>      endif
>>  endif
>> --
>> 2.8.1
> 
> 
> .
> 

Re: [dpdk-dev] [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3

[Ruifeng Wang]

> -----Original Message-----
> From: fengchengwen <fengchengwen@huawei.com>
> Sent: Monday, June 28, 2021 11:56 AM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
> ferruh.yigit@intel.com
> Cc: dev@dpdk.org; bruce.richardson@intel.com;
> vladimir.medvedkin@intel.com; viktorin@rehivetech.com;
> jerinj@marvell.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; jerinjacobk@gmail.com;
> juraj.linkes@pantheon.tech; nd <nd@arm.com>
> Subject: Re: [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3
> 
> On 2021/6/28 11:33, Ruifeng Wang wrote:
> >> -----Original Message-----
> >> From: Chengwen Feng <fengchengwen@huawei.com>
> >> Sent: Monday, June 28, 2021 10:58 AM
> >> To: thomas@monjalon.net; ferruh.yigit@intel.com; Ruifeng Wang
> >> <Ruifeng.Wang@arm.com>
> >> Cc: dev@dpdk.org; bruce.richardson@intel.com;
> >> vladimir.medvedkin@intel.com; viktorin@rehivetech.com;
> >> jerinj@marvell.com; Honnappa Nagarahalli
> >> <Honnappa.Nagarahalli@arm.com>; jerinjacobk@gmail.com;
> >> juraj.linkes@pantheon.tech
> >> Subject: [PATCH 2/2] net/hns3: fix SVE code compile error with gcc8.3
> >>
> >> If the target machine has SVE feature (e.g. '-march=armv8.2-a+sve'),
> >> and compiler are gcc8.3, it will compile error, the error is
> >> arm_sve.h no such file or directory.
> >>
> >> The solution:
> >> a. If RTE_HAS_SVE_ACLE defined (it means the minimum instruction set
> >> support SVE ACLE) then compiles it.
> >> b. Else if the compiler support SVE ACLE then compiles it.
> >> c. Otherwise don't compile it.
> >>
> >> Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx")
> >> Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx")
> >> Cc: stable@dpdk.org
> >>
> >> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
> >> Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
> >> ---
> >>  drivers/net/hns3/hns3_rxtx.c |  2 +-  drivers/net/hns3/meson.build |
> >> 20 +++++++++++++++++++-
> >>  2 files changed, 20 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/net/hns3/hns3_rxtx.c
> >> b/drivers/net/hns3/hns3_rxtx.c index cb9eccf..a86e105 100644
> >> --- a/drivers/net/hns3/hns3_rxtx.c
> >> +++ b/drivers/net/hns3/hns3_rxtx.c
> >> @@ -2811,7 +2811,7 @@ hns3_get_default_vec_support(void)
> >>  static bool
> >>  hns3_get_sve_support(void)
> >>  {
> >> -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE)
> >> +#if defined(RTE_HAS_SVE_ACLE)
> >>  	if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256)
> >>  		return false;
> >>  	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE))
> >> diff --git a/drivers/net/hns3/meson.build
> >> b/drivers/net/hns3/meson.build index 53c7df7..a99e0db 100644
> >> --- a/drivers/net/hns3/meson.build
> >> +++ b/drivers/net/hns3/meson.build
> >> @@ -35,7 +35,25 @@ deps += ['hash']
> >>
> >>  if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64')
> >>      sources += files('hns3_rxtx_vec.c')
> >> -    if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> >> +
> >> +    # compile SVE when:
> >> +    # a. support SVE in minimum instruction set baseline
> >> +    # b. it's not minimum instruction set, but compiler support
> >> +    if dpdk_conf.has('RTE_HAS_SVE_ACLE')
> >>          sources += files('hns3_rxtx_vec_sve.c')
> >> +    elif cc.has_argument('-march=armv8.2-a+sve') and
> >> cc.check_header('arm_sve.h')
> >> +        cflags += ['-DRTE_HAS_SVE_ACLE=1']
> >> +        sve_cflags = []
> > Global cflags will be changed here. I think it is not very good as build of
> other parts could be without SVE support.
> > How about " sve_cflags = ['-DRTE_HAS_SVE_ACLE=1']" and drop changes to
> cflags?
> > In this way, the additional flag will be limited to hns3_sve_lib.
> 
> This will not change global cflags: the cflags was independent from other
> drives [implemented in drivers/meson.build] And I also check the
> 'build.ninja' and found the RTE_HAS_SVE_ACLE only defined with hns3 driver
> source file.
> PS: hns3_rxtx.c also refer the marco 'RTE_HAS_SVE_ACLE'.
> 
Thanks for the explanation. I see cflags is restored for each driver.
Looks good to me. My tag was already added.

> >
> >> +        foreach flag: cflags
> >> +            if not (flag.startswith('-march=') or
> >> + flag.startswith('-mcpu=') or
> >> flag.startswith('-mtune='))
> >> +                sve_cflags += flag
> >> +            endif
> >> +        endforeach
> >> +        hns3_sve_lib = static_library('hns3_sve_lib',
> >> +                        'hns3_rxtx_vec_sve.c',
> >> +                        dependencies: [static_rte_ethdev],
> >> +                        include_directories: includes,
> >> +                        c_args: [sve_cflags, '-march=armv8.2-a+sve'])
> >> +        objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c')
> >>      endif
> >>  endif
> >> --
> >> 2.8.1
> >
> >
> > .
> >

Re: [dpdk-dev] [PATCH 0/2] bugfix for SVE compile

[fengchengwen]

Hi, Thomas

Please review this patch set, thanks.

PS: this patch set already reviewed by ARM guys, and the CI has some
errors, but it seem not related to this patch set.


On 2021/6/28 10:57, Chengwen Feng wrote:
> This patch set contains two bugfixes for SVE compile.
> Note:
> 1) Because 2/2 patch needs backport to 20.11 so we separate it.
> 2) These two patches already acked by ARM guys from previous threads.
> 
> Chengwen Feng (2):
>   build: fix SVE compile error with gcc8.3
>   net/hns3: fix SVE code compile error with gcc8.3
> 
>  config/arm/meson.build         |  6 ++++++
>  drivers/net/hns3/hns3_rxtx.c   |  2 +-
>  drivers/net/hns3/meson.build   | 20 +++++++++++++++++++-
>  lib/eal/arm/include/rte_vect.h |  2 +-
>  lib/lpm/rte_lpm.h              |  2 +-
>  5 files changed, 28 insertions(+), 4 deletions(-)
> 

Re: [dpdk-dev] [PATCH 1/2] build: fix SVE compile error with gcc8.3

[Thomas Monjalon]

28/06/2021 04:57, Chengwen Feng:
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -488,3 +488,9 @@ if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
>      compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
>      'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
>  endif
> +
> +# Check whether SVE ACLE is supported and set the corresponding flag which will used with SVE ACLE code.
> +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> +        cc.check_header('arm_sve.h'))
> +    dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> +endif

Simpler and better sorted:

--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -524,6 +524,9 @@ endif
 
 if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
     compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
+    if (cc.check_header('arm_sve.h'))
+        dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
+    endif
 endif

Re: [dpdk-dev] [PATCH 0/2] bugfix for SVE compile

[Thomas Monjalon]

28/06/2021 04:57, Chengwen Feng:
> This patch set contains two bugfixes for SVE compile.
> Note:
> 1) Because 2/2 patch needs backport to 20.11 so we separate it.
> 2) These two patches already acked by ARM guys from previous threads.
> 
> Chengwen Feng (2):
>   build: fix SVE compile error with gcc8.3
>   net/hns3: fix SVE code compile error with gcc8.3

Applied with proposed improvement, thanks.